Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed December 5, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 7, 12
b. Pending: 1-20
Claims 1, 3, 7, 9, and 18 have been amended through preliminary amendments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 2, 3, 8, and 9 are objected to because of the following informalities:
Regarding claims 2 and 8, make the following change:
“during the scrubbing operation”
Regarding claims 3 and 9, make the following change:
“[[UE]]an uncorrectable error (UE) flag”
Regarding claim 9, “generating UE flag in which the scrubbing operation is performed” does not make sense. Examiner instead recommends “generating an uncorrectable error (UE) flag during the scrubbing operation”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claims 1, 7, and 12 all disclose determining a fail row and also generating an address of a fail row. The Examiner is unsure how the latter is distinct from the former. How is the generation of the fail row address by the row fail detector different from the determination of the fail row? The Examiner assumes that a determination of a fail row requires the determination of the address of the fail row. Thus independent claims 1, 7, and 12, and dependent claims 2-6, 8-11, and 13-20, which depends on the independent claims, are thus rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12, 14-15, and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bains et al. (US Pub. 20240211344 A1; “Bains”).
Regarding independent claim 1, Bains discloses a memory device (Fig. 2: system 200; [0057]), comprising:
a memory cell array (array 262; [0059]) including memory cells arranged in a plurality of rows ([0059]: Array 262 represents memory cells within memory device 260. Array 262 can include multiple rows of memory);
an error correction code (ECC) engine (error checking and scrubbing (ECS) 270; [0060]) configured to read a codeword from the memory cell array and detect one or more error bits in the codeword in a scrubbing operation on the memory cell array ([0212]: error correction in read path 1734 can include the application of an XOR (exclusive OR) tree to a corresponding H matrix to detect errors and selectively correct errors (in the case of a single bit error)…linear combinations of digits of the codeword equal zero. Thus, the H matrix rows identify the coefficients of parity check equations that must be satisfied for a component or digit to be part of a codeword) in response to a refresh command ([0070]: memory controller 210 simply needs to provide refresh commands for memory device 260 to manage ECS operations in automatic mode);
a row fail detector (Fig. 1: block 132, TF 136, error counter (EC) 142, and errors per row counter (EPRC) 144; [0050]. The following explains that Fig. 2 can use the error scrubbing engine of Fig. 1: [0057]: System 200 includes an error scrubbing engine in accordance with system 100 of FIG. 1) configured to:
determine a fail row based on a number of the one or more error bits in the codeword in the scrubbing operation ([0050]: EC 142 only increments to count rows having at least one error; [0051]: In one example, TF 136 is set when the threshold filter count equals an error threshold count (ETC). The ETC represents a configurable threshold set by the system or by the user to only count errors in response to a threshold number. The threshold can be per row), and
generate a fail row address indicating an address of the fail row among the plurality of rows ([0053]: EPRC 144 counts errors to indicate a row with the highest number of errors in the block of addresses being scrubbed); and
a flag generator configured to store the fail row address in a register ([0055]: EPR & address 164 represents a register or storage location to store the error count and address for a row having the highest number of errors).
Regarding claim 2, Bains discloses the limitations of claim 1.
Bains further discloses:
wherein the flag generator is configured to store the fail row address in the register ([0055]) within the scrubbing operation ([0081]: command execution 334 generates internal operations to perform within memory 330 related to ECC and error scrubbing. Command execution 334 can generate commands for the internal operations, which can include a series of ECC operations for the memory device to perform in ECS mode to record error count information. In one example, mode register 336 includes one or more multipurpose registers to store error count information).
Regarding claim 3, Bains discloses the limitations of claim 1.
Bains further discloses:
wherein the flag generator is configured to generate UE flag ([0038]: the ECS operations include operations related to detection of uncorrectable errors and reporting the uncorrectable errors such as indication to the host; also see [0213]).
Regarding claim 4, Bains discloses the limitations of claim 1.
Bains further discloses:
wherein the row fail detector (Fig. 1: 132, 136, 142, 144) is further configured to track the number of the one or more error bits in the codeword included in each of the plurality of rows in which the scrubbing operation is performed ([0053]; also, in reference to Fig. 3, per [0086]: ECS control 350 includes single bit error (SBE) count 352 of rows 342, which can represent a total number of SBEs detected and corrected…ECS control 350 includes max count (CNT)/address (ADDR) 354 to represent a register that stores a count of errors in the row with the most errors per row, and the address of the row…In one example, ECS control 350 includes more counters).
Regarding claim 5, Bains discloses the limitations of claim 4.
Bains further discloses:
wherein the row fail detector (Fig. 1: 132, 136, 142, 144) is further configured to determine whether the number of the one or more error bits in the codeword included in each of the plurality of rows in which the scrubbing operation is performed is greater than a value ([0054]: EPRC 144 provides its count to high error count 152, as well as providing its count for comparison to a previous high or maximum error count from error count 152. High error count 152 represents a register or other storage that holds a high error count indicating the maximum number of errors detected in any of the rows. Comparison logic 150 determines if the count value in EPRC 144 is greater than high error count 152).
Regarding claim 6, Bains discloses the limitations of claim 1.
Bains further discloses:
wherein the flag generator is further configured to generate a flag while or after performing the scrubbing operation ([0038]: the scrubbing operations are described below as ECS operations, referring to operations that check for errors, correct correctable errors that are found (correct detected errors), and write corrected data back to memory. In one example, the ECS operations include the performance of error counting in a system that performs scrubbing with transparency or insight into the number of errors. In one example, the ECS operations include operations related to detection of uncorrectable errors and reporting the uncorrectable errors such as indication to the host).
Independent claim 7 is substantially the same in claimed subject matter as claim 1 except for being drafted in method format instead of device format and is rejected for the same reasons as independent claim 1.
Regarding claims 8-10, Bains discloses all the limitations of claim 7. Claims 8-10 recite substantially the same limitations as claims 2, 3, and 4, respectively, and henceforth are rejected for the same reasons.
Regarding claim 11, Bains discloses all the limitations of claim 10. Claim 11
recites substantially the same limitations as claim 5, and henceforth is rejected for the
same reasons.
Independent claim 12 contains first through fifth limitations that are substantially the same in claimed subject matter as independent claim 1 and thus those limitations are rejected for the same reasons as independent claim 1. Further, through Bains:
a scrubbing operation during a refresh operation ([0082]: refresh control 338 can trigger ECS operations when in self-refresh mode. In one example, refresh control 338 can trigger ECS operations in response to all bank refresh commands);
a flag generator configured to generate a first flag which indicates that the plurality of rows includes the fail row ([0050]: block 132, TF 136, and error counter (EC) 142 count errors per row, and EC 142 only increments to count rows having at least one error. In one example, block 132, TF 136, and error counter (EC) 142 count the total number of errors, and EC 142 increments to count every error found by ECC logic 130).
Regarding claim 14, Bains discloses all the limitations of claim 12. Claim 14
recites substantially the same limitations as claims 2 and 8, and henceforth is rejected for the same reasons.
Regarding claim 15, Bains discloses the limitations of claim 14.
Bains further discloses:
wherein the fail row address is transmitted to a memory controller ([0056]: The providing of error count 162 and EPR & address 164 can be referred to as providing error transparency or as transparency data. The transparency data provides insight for the host or the memory controller into errors within the memory) in response to a command issued by the memory controller ([0070]: Manual ECS mode can refer to a mode in which ECS operations are managed by memory controller 210, where memory controller 210 is responsible for sending ECS commands to memory device 260. Automatic ECS mode can refer to a mode in which ECS operations are managed internally by memory device 260 during refresh…memory controller 210 simply needs to provide refresh commands for memory device 260 to manage ECS operations in automatic mode).
Regarding claim 17, Bains discloses the limitations of claim 12.
Bains further discloses:
wherein the ECC engine (Fig. 2: 270) is configured to detect and correct the one or more error bits in the codeword read from the memory cell array ([0212]) during the refresh operation ([0082]) in response to a refresh command ([0070]).
Regarding claim 18, Bains discloses all the limitations of claim 12. Claim 18
recites substantially the same limitations as claims 3 and 9, and henceforth is rejected for the same reasons.
Regarding claim 19, Bains discloses the limitations of claim 12.
Bains further discloses:
wherein the scrubbing operation is set by programing a mode register ([0077]: memory controller 320 can set a mode (e.g., via register or mode register) within memory 330 to trigger the memory to generate addresses and control the execution of scrub operations).
Regarding claim 20, Bains discloses all the limitations of claim 12. Claim 20
recites substantially the same subject matter as the fifth limitation of independent claim 1, and henceforth is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable
over Bains (US Pub. 20240211344 A1) as applied to claim 12 above, and
further in view of Cha et al. (US Pub. 20170139641 A1; “Cha”).
Regarding claim 13, Bains discloses the limitations of claim 12. Bains does not disclose:
wherein the first flag is transmitted to a memory controller in response to a command issued by the memory controller.
However, Cha teaches:
wherein the first flag is transmitted to a memory controller in response to a command issued by the memory controller ([0080]: the scrubbing request signal generator 490 provides the scrubbing request signal SRS to the memory controller 100…according to the mode signal MS in response to one of the first detection signal DET1 and the second detection signal DET2; [0077]: the control logic circuit 210a may provide the scrubbing request signal generator 490 with a mode signal MS designating a scrubbing mode).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Cha to Bains wherein the first flag is transmitted to a memory controller in response to a command issued by the memory controller in order to implement an STT-MRAM with reduced cell size, prevent write disturbance, and improve read operations (Cha, [0052]).
Regarding claim 16, Bains discloses the limitations of claim 12. Bains discloses a flag generator, but does not disclose:
wherein the flag generator is configured to output the first flag while or after performing the scrubbing operation.
However, Cha teaches:
wherein the flag generator (Fig. 2: scrubbing request signal generator 490; [0060]) is configured to output the first flag while or after performing the scrubbing operation ([0080]; [0077]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cha to modified Bains wherein the flag generator is configured to output the first flag while or after performing the scrubbing operation in order to implement an STT-MRAM with reduced cell size, prevent write disturbance, and improve read operations (Cha, [0052]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Song et al. (US Pub. 20210142860 A1): paras. [0032], [0035], and [0088], and Figs. 1, 2, and 14 are relevant to claims 1, 7, and 12.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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/E.R.A./Examiner, Art Unit 2824
6/24/2026
/Richard Elms/Supervisory Patent Examiner, Art Unit 2824
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