DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (CN202211376117.0 People’s Republic of China 11/04/2022).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 11/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “a second control circuit…” as recited in claim 14, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-3, 9-11, 14’s “first-stage/second-stage amplifier circuit”, “an equalizer circuit”, “a first/second control circuit” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 11 recites the limitation "wherein the control circuit" in the claim 11. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 15 are rejected under both 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 8,027,193 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Lee, for example in Figs. 1-8, discloses a memory (see for example in Fig. 4 related in Figs. 1-3, 5-8), comprising:
a first-stage amplifier circuit (e.g., circuit 13; in Fig. 4 related in Figs. 1-3, 5-8), connected to a bit line and a complementary bit line (e.g., BL and BLB; in Fig. 4 related in Figs 1-3, 5-8), and configured to amplify a voltage difference between the bit line and the complementary bit line (implied the BLSA’s function; in Fig. 4 related in Figs. 1-3, 5-8);
a second-stage amplifier circuit (e.g., circuit 19; in Fig. 4 related in Figs. 1-3, 5-8), connected to a local data line and a complementary local data line (e.g., LIO and LIOB; in Fig. 4 related in Figs. 1-3, 5-8), further connected to a global data line and a complementary global data line (e.g., GIO and GIOB; in Fig. 4 related in Figs. 1-3, 5-8), amplifying a voltage difference between the local data line and the complementary local data line after the local data line is connected to the bit line and the complementary local data line is connected to the complementary bit line (see for example in Fig. 4 related in Figs. 1-3, 5-8), and generating a voltage difference between the global data line and the complementary global data line (see for example in Fig. 4 related in Figs. 1-3, 5-8); and
a driving circuit (e.g., circuit 18; in Fig. 4 related in Figs. 1-3, 5-8), connected to the local data line and the complementary local data line, and amplifying the voltage difference between the local data line and the complementary local data line (see for example in Fig. 4 related in Figs. 1-3, 5-8).
The structure in of the prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.1(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, Lee, for example in Figs. 1-8, discloses wherein the memory further comprises: an equalizer circuit, connected to the local data line and the complementary local data line (e.g., circuit 18b; in Fig. 4 related in Figs. 1-3, 5-8), and charging voltages on the local data line and the complementary local data line to a precharge voltage before the local data line is connected to the bit line and the complementary local data line is connected to the complementary bit line (e.g., from a level of internal power voltage AV to PM1; in Figs. 2, 4 related in Figs. 1, 3, 5-8); and the driving circuit is configured to amplify the voltage difference between the local data line and the complementary local data line after the voltages on the local data line and the complementary local data line are charged to the precharge voltage (see for example in Figs. 2, 4 related in Figs. 1, 3, 5-8). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, Lee, for example in Figs. 1-8, discloses wherein a start moment at which the driving circuit amplifies the voltage difference between the local data line and the complementary local data line is earlier than a start moment at which the second-stage amplifier circuit amplifies the voltage difference between the local data line and the complementary local data line (see for example in Figs. 2, 4 related in Figs. 1, 3, 5-8, as discussed above). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, Lee, for example in Figs. 1-8, discloses wherein a first start moment is in a first value range when a first time interval is in a first time range; the first start moment is in a second value range when the first time interval is in a second time range (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); the first time interval is a time interval between adjacent row addressing and column addressing of the memory, and the first start moment is a start moment at which the driving circuit amplifies the voltage difference between the local data line and the complementary local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); and an upper limit value of the first time range is less than or equal to a lower limit value of the second time range, and an upper limit value of the first value range is greater than or equal to a lower limit value of the second value range (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, Lee, for example in Figs. 1-8, discloses wherein the driving circuit is configured to: amplify the voltage difference between the local data line and the complementary local data line by driving a voltage on the local data line and/or a voltage on the complementary local data line upward (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); and a driving capability of driving the local data line upward is negatively correlated with the voltage on the complementary local data line, and a driving capability of driving the complementary local data line upward is negatively correlated with the voltage on the local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, Lee, for example in Figs. 1-8, discloses wherein the driving circuit comprises: a switch unit, connected to a first driving unit and a second driving unit (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above), controlling connection or disconnection between the first driving unit and a first power supply terminal under the control of a first control signal (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above), and controlling connection or disconnection between the second driving unit and the first power supply terminal under the control of the first control signal, the first power supply terminal providing a power voltage (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); the first driving unit, connected to the local data line and the complementary local data line, and driving the voltage on the local data line upward based on the voltage on the complementary local data line when the first driving unit is connected to the first power supply terminal (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); and the second driving unit, connected to the local data line and the complementary local data line, and driving the voltage on the complementary local data line upward based on the voltage on the local data line when the second driving unit is connected to the first power supply terminal (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); and a driving capability of the first driving unit in driving the local data line is negatively correlated with the voltage on the complementary local data line, and a driving capability of the second driving unit in driving the complementary local data line is negatively correlated with the voltage on the local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, Lee, for example in Figs. 1-8, discloses wherein the first driving unit comprises: a first P-type transistor, a source being connected to the switch unit, a drain being connected to the local data line, and a gate being connected to the complementary local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); and the second driving unit comprises: a second P-type transistor, a source being connected to the switch unit, a drain being connected to the complementary local data line, and a gate being connected to the local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, Lee, for example in Figs. 1-8, discloses wherein the switch unit comprises: a third P-type transistor, a source being connected to the first power supply terminal, a drain being connected to the source of the first P-type transistor, the drain being further connected to the source of the second P-type transistor, and a gate receiving the first control signal (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 15, Lee, for example in Figs. 1-8, discloses wherein the memory further comprises: a third-stage amplifier circuit (e.g., circuit 21; in Fig. 4 related in Figs. 1-3, 5-8), connected to the global data line and the complementary global data line, and configured to amplify the voltage difference between the global data line and the complementary global data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above). Also, the structure of in prior art (Lee) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 8,027,193 B2 hereinafter “Lee_1”) in view of Lee et al (US 11,776,588 B2 hereinafter “Lee_2”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 9, Lee, for example in Figs. 1-8, discloses wherein the driving circuit further comprises: a first output terminal being connected to a control terminal of the switch unit (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above), a second output terminal being connected to a control terminal of the second-stage amplifier circuit, and a first input terminal receiving a mode signal and a second input terminal receiving a reference signal to generate the first control signal based on the mode signal and the reference signal and generate a second control signal based on the reference signal (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above); and a start moment at which the first control signal is in a valid state is earlier than a start moment at which the second control signal is in a valid state, and the second-stage amplifier circuit is controlled by the second control signal to amplify the voltage difference between the local data line and the complementary local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8, as discussed above).
However, Lee_1 is silent with regard to a first control circuit.
In the same field of endeavor, Lee_2, for example in Figs. 1-13, discloses a first control circuit (e.g., control logic circuit 150; in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Lee_1 such as semiconductor memory device having bit line disturbance preventing unit (see for example in Figs. 1-8 of Lee_1) by incorporating the teaching of Lee_2 such as sense amplifier and semiconductor memory device including the sense amplifier (see for example in Figs. 1-13 of Lee_2), for the purpose of controlling the peripheral circuit includes a sense amplifier for amplifying a voltage difference between a bit line BL and a complementary bit line BLB (Lee_2, Col. 1, lines 31-33).
The structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.1(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, the above Lee_1/Lee_2, combination discloses wherein the start moment at which the first control signal is in the valid state is later than an end moment at which an equalization control signal is in a valid state (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above), and the voltages on the local data line and the complementary local data line are charged to a precharge voltage when the equalization control signal is in the valid state (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.1(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 11, the above Lee_1/Lee_2, combination discloses wherein the control circuit is configured to: determine a time step between the reference signal and the first control signal based on the mode signal; and process the reference signal based on the time step to generate the first control signal (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.1(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, the above Lee_1/Lee_2, combination discloses wherein the mode signal is determined based on any one or more parameters of a first time interval, a process angle of the memory, a temperature of the memory, and an operating voltage of the memory (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above); and the first time interval is a time interval between adjacent row addressing and column addressing of the memory (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.1(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, the above Lee_1/Lee_2, combination discloses wherein the reference signal is a column selection signal, and the column selection signal is configured to control connection or disconnection between the bit line and the local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above), and is further configured to control connection or disconnection between the complementary bit line and the complementary local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.1(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, the above Lee_1/Lee_2, combination discloses wherein the memory further comprises: a second control circuit, connected to the bit line and the complementary bit line, further connected to the local data line and the complementary local data line (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above), and configured to receive a column selection signal, control connection or disconnection between the bit line and the local data line under the control of the column selection signal, and control connection or disconnection between the complementary bit line and the complementary local data line under the control of the column selection signal (see for example in Figs. 2, 4, 7 related in Figs. 1, 3, 5-6, 8 of Lee_1 and also see in Figs. 3, 6 related in Figs. 1-2, 4-5, 7-13 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.1(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 05/29/2026
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