Prosecution Insights
Last updated: April 18, 2026
Application No. 18/950,562

STRUCTURING SEGMENTS OF A SEGMENT GROUP STORED VIA A COMPUTING SYSTEM

Non-Final OA §102
Filed
Nov 18, 2024
Examiner
KERVEROS, DEMETRIOS C
Art Unit
2111
Tech Center
2100 — Computer Architecture & Software
Assignee
Ocient Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
90%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
933 granted / 1069 resolved
+32.3% vs TC avg
Minimal +3% lift
Without
With
+2.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
30 currently pending
Career history
1099
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
8.4%
-31.6% vs TC avg
§102
50.1%
+10.1% vs TC avg
§112
27.6%
-12.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1069 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a NON-FINAL OFFICE ACTION in response to the present Application filed 11/18/2024. Claims 1-20 are pending in the Application, of which Claims 1, 19 and 20 are independent. Continuity/ Priority Information The present Application 18950562, filed 11/18/2024 is a Continuation of 18543867, filed 12/18/2023, now U.S. Patent No. 12,182,121, which is a Continuation of 18166103, filed 02/08/2023, now U.S. Patent No. 11,893,018, which is a Continuation of 17679835, filed 02/24/2022, now U.S. Patent No. 11,609,912, which is a Continuation of 17091195, filed 11/06/2020, now U.S. Patent No. 11,294,902, which is a Continuation of 16267676, filed 02/05/2019, now U.S. Patent No. 10,866,954, and Claims Priority from Provisional Application 62745787, filed 10/15/2018 Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/18/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eda et al. (Pub. No. US 20190379400) Pub. Date: 2019-12-12. Regarding independent Claims 1, 19 and 20, Eda discloses methods and systems for location selection for storing data based on erasure code techniques, comprising: at least one processor; and at least one memory that stores operational instructions that, when executed by the at least one processor, [0041] FIG. 1 is a diagram illustrating one embodiment of a system 100 for storing data in a storage device. The system 100 includes, among other components, a processor 102 coupled to several input/output devices 106 and one or more storage devices 104. cause the computing system to perform operations that include: [0042] In certain embodiments, the processor 102 may be a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus. As described herein, the processor 102 may execute computer-readable program instructions associated with selecting locations for storing data on a storage device 104 based on erasure code techniques associated with applications executed by the processor 102. generating a set of segments of a segment group, wherein each segment of the set of segments includes: a data and parity section that includes a corresponding set of sorted data slabs; [0061] For example, as illustrated in FIG. 3A, a storage controller 108 may randomly assign locations on a storage device 104 for storing particular types of data. For example, a storage controller 108 may randomly store data segments and parity segments in different locations on a drive. [0062] In certain embodiments, the storage controller 108 may store data segments on an outer track of the third disk 306 which has a data transfer speed of 70 MB per second. Also, the storage controller 108 may store a parity segment on an outer track of the eighth disk 316, where erasure code techniques that use the parity segment for erasure coding may not benefit from faster storage device locations as compared to the benefit available to data segments. a data and parity section that includes a corresponding set of sorted data slabs; [0067] For example, as illustrated in FIG. 3D, a storage controller 108 may assign locations on a storage device 104 for storing particular types of data based on data transfer speeds and erasure code techniques. For example, a storage controller 108 may store data segments and parity segments in different locations on a drive. As illustrated, a disk drive may have multiple disks that are capable of transferring data at different speeds. For example, a disk drive may include a first drive 302, a second drive 304, a third drive 306, a fourth drive 308, a fifth drive 310, a sixth drive 312, a seventh drive 314, and an eighth drive 316. a manifest section that includes metadata; and at least one index section that includes index data for the corresponding set of sorted data slabs; [0048] In at least one embodiment, the erasure code technique database 118 may store information describing the trade-offs and benefits associated with the different methods of performing erasure coding. In at least one embodiment, the storage device 104 may also store a storage device location database 128. The storage device location database 128 may, in certain embodiments, store information regarding which locations on a storage device currently store data. a statistics section that includes statistical information regarding the each segment; [0069] FIG. 4 depicts a storage controller 108. Additionally, the classification module 112 may include a disk statistics module 420. [0070] The disk statistics module 420, is configured to save speed characteristics for different locations within a storage device, such as the storage device 104. For example, where the storage device 104 is a hard disk drive, having multiple disks, the disk statistics module 420 may determine the data transfer speeds for the different disks. Further, the disk statistics module 420 may also determine the data transfer speeds for different locations on a single disk based on whether the location is at an inner track or an outer track on the disk. storing the set of segments of the segment group across a plurality of computing devices of a storage cluster of the computing system. [0070] For example, the disk statistics module 420 may store data in a data speed database that indicates that storage device addresses associated with inner track locations have slower data transfer speeds than storage device addresses associated with outer track locations. In at least one embodiment, the disk statistics module 420 may store information regarding the difference in data transfer speeds between different locations on a disk or between different disks. Regarding Claims 2-4, Eda discloses generate a plurality of lines of coding blocks that includes a plurality of data blocks and a plurality of parity blocks; [0076] FIG. 7 depicts an embodiment of a method 700 for classifying information to be stored on a storage device. For example, the classification module 112 may identify the erasure code technique associated with the data chunk corresponding to “data blocks” based on the application that is associated with the data chunk“ data blocks”. In at least one implementation, the classification module 112 may tag the data chunk by data type. For instance, the classification module 112 may tag the data chunk “data blocks” as a data segment or parity data. Regarding Claim 5, Eda discloses the fixed segment size is 32 Giga-Bytes. [0046] In some embodiments, a storage device 104 stores objects. In at least one embodiment, the storage device 104 stores a data speed database 116. A data speed database 116, as described herein, may refer to a data structure that stores data transfer speeds for particular locations in the storage device 104. Regarding Claims 6-8, Eda discloses the data and parity section is generated to include the sorted data slabs. [0053] In a further embodiment, the classification module 112 may identify that an erasure code technique associated with data to be stored on the storage device 104 is a parity array code. As part of the parity array code, parity data may be used to correct errors in the information stored on the storage device 104. In certain embodiments, parity data may not benefit from being stored in storage device locations having faster data transfer speeds as compared to erasure code techniques that reconstruct data from data stored on the storage device 104. As parity array codes can be stored in locations having slower data transfer speeds, the classification module 112 may identify the data to be stored on the storage device 104. Regarding Claim 9, Eda discloses the corresponding set of sorted data slabs is redundancy encoded in accordance with at least one of: RAID 5, 6,10 encoding. [0057] FIG. 2 is a block diagram illustrating a comparison of a conventional RAID storage device 200 to a declustered RAID storage device 201. As described above, the storage device 104 may be implemented as a conventional RAID storage device 200. Alternatively, the storage device 104 may be a declustered RAID storage device 201. Regarding Claims 10-14, Eda discloses wherein the corresponding set of sorted data slabs is generated from a plurality of rows that each include column values of a plurality of columns, and wherein the corresponding set of sorted data slabs includes the column values for a subset of the plurality of columns. [0058] In contrast to the conventional RAID storage device 200, the declustered RAID storage device 201 may spread the data across the multiple discs in the storage device 104. For example, to decluster the data in a conventional RAID storage device 200, the RAID storage device 200 may be divided into the first storage array 202, the second storage array 204, and the third storage array 206. The first storage array 202, second storage array 204, and a third storage array 206 may be divided into seven tracks, where there are two strips per array. The different strips from the different arrays may then be combinatorially spread across the different disk positions. For example, the strips of the first storage array 202 may be combinatorially spread across the seven disk positions as illustrated in first virtual disk 216. The strips of the second storage array 204 may be combinatorially spread across the seven disk positions as illustrated in second virtual disk 218. Regarding Claim 15, Eda discloses wherein the statistical information includes at least one of: a number of rows of the plurality of rows included in at least one of the set of sorted data slabs of the each segment; [0070] The disk statistics module 420, in one embodiment, is configured to save speed characteristics for different locations within a storage device, such as the storage device 104. As used herein, the speed characteristics may refer to the data transfer speeds for different locations on a storage device. For example, where the storage device 104 is a hard disk drive, having multiple disks, the disk statistics module 420 may determine the data transfer speeds for the different disks. Regarding Claims 16-18, Eda discloses wherein the metadata included in the manifest section includes descriptive metadata that includes at least one of: name information, abstract information, keyword information, or author information. [0047] In certain embodiments, a storage device 104 may also store information regarding erasure code techniques in an erasure code technique database 118. In certain implementations an erasure code technique database 118 may store information regarding erasure code techniques such as benefits and deficiencies of different erasure code techniques, storage device location characteristics that the benefits particular erasure code techniques, or the like. Prior Art References Cited The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form. US 20170147265 Kingdon et al. Abstract. A disclosed method is performed at a fault-tolerant object-based storage system configured to synthesize parity data in order to protect stored data from loss, the fault-tolerant object storage system including a plurality of storage entities each configured to store data on an object-basis. US 20130339818 CARPENTIER et al. [0054] Next, in step 420 the first node to store the first data segment of the object will be designated and this node will perform a number steps in order to prepare for erasure coding of the object into the data and parity segments on the different nodes. For instance, the SAN will choose unique identifiers for all of the data and parity segments in the erasure set (e.g., using a random number generator), will set up chunked encoded POSTS to the M node recipients, and will determine a maximum segment size at the beginning of the write which will limit the size of this erasure set. US 20130036340 Kidney et al. Abstract A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAMES C KERVEROS/Primary Examiner, Art Unit 2111 Date: April 1, 2026 Non-Final Rejection 20260326 JAMES C. KERVEROS Primary Examiner, Art Unit 2111 James.Kerveros@USPTO.GOV
Read full office action

Prosecution Timeline

Nov 18, 2024
Application Filed
Mar 27, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12601785
PROVIDING CONFIGURABLE SECURITY FOR INTELLECTUAL PROPERTY CIRCUITS OF A PROCESSOR
2y 5m to grant Granted Apr 14, 2026
Patent 12602167
DATA PROCESSING METHOD AND APPARATUS, DEVICE, AND READABLE STORAGE MEDIUM
2y 5m to grant Granted Apr 14, 2026
Patent 12591492
DATA PROCESSING NETWORK FOR DATA PROCESSING
2y 5m to grant Granted Mar 31, 2026
Patent 12586655
MEMORY FAILURE ANALYSIS BASED ON BITLINE THRESHOLD VOLTAGE DISTRIBUTIONS
2y 5m to grant Granted Mar 24, 2026
Patent 12566651
ERROR DETECTION FOR ENCRYPTION OR DECRYPTION KEYS
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
90%
With Interview (+2.6%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 1069 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month