DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on January 6, 2025 has been considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,857,973 B1 to Kwanyeob Chae, et al. (hereafter Chae) in view of US 20050157827 A1 to Yong-Jin Yoon, et al. (hereafter Yoon).
Regarding Independent Claim 1, Chae discloses a command sampling circuit, comprising:
a sampling circuit (Sampling Circuit 210: Chae, Figure 2) and a delay circuit (Delay circuit 215: Chae, Figure 2),
wherein the sampling circuit
receives a memory command (Receiving a memory command: Chae, col.5:26-29) and a sampling clock (Data strobe signal DQS: Chae, col.5:28), and
is configured to sample the memory command (Capturing the logic state of the data signal: Chae, col.5:26-27) separately in response to
a first sampling edge (Rising edge: Chae, col.5:30-32) and a second sampling edge of the sampling clock (Falling edge: Chae, col.5:35-39), and
output a first cycle command (First data output DOUT: Chae, Figure 2) and a second cycle command (Second data output WR: Chae, Figure 2);
the sampling circuit has a first output end and a second output end (The Sampling circuit having two outputs, DOUT and WR: Chae, Figure 2);
an input end of the delay circuit is connected to the first output end of the sampling circuit (The input of delay circuit 225 being one of the outputs of the sampling circuit: Chae, Figure 2),
an output end of the delay circuit is connected to a command decoding circuit (The output of delay circuit being fed to FIFO2: Chae, Figure 2), and
the delay circuit is configured to
delay a command output at the first output end of the sampling circuit and then output a delayed command (Delaying the WR signal to generate WRd: Chae, col.6:9-13);
the command decoding circuit (The second FIFO circuit: Chae, Figure 2)
is coupled to the command sampling circuit (FIFO2 coupled to the sampling circuit: Chae, Figure 2),
receives an output clock (FIFO2 receiving WRd: Chae, Figure 2), and
is configured to decode the commands output by the sampling circuit (Decoding DOUT: Chae, col.6:14), and
output, in response to an output edge of the output clock (Sampling DOUT in response to an edge of WRd: Chae, col.6:14-18),
a current decoded result as decoding information of the memory command (The output data being a result of decoding the input data: Chae, col.6:14-18);
the second output end of the sampling circuit is connected to an address output circuit (A second output of the sampling circuits being fed into a separate FIFO circuit: Chae, Figure 12);
the address output circuit receives the output clock and is configured to output, in response to the output edge, a command currently output at the second output end of the sampling circuit as address information of the memory command (Operations of the second FIFO circuit mimicking the operation of the first FIFO circuit: Chae, col.14:46-56).
Chae expressly discloses the core sampling circuit claimed by applicant, as outlined above. Minor differences, such as the command signal being delayed after the sampling circuit rather than separately from the circuit, are simple substitutions of one structure with another with predictable results, as seen in the following amended illustration:
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Chae, however, is directed towards data sampling and multi-rank FIFO interfacing and does not expressly disclose a first delayed data path and second data path, wherein both paths output their respective outputs in response to the same output clock edge. Yoon, however, discloses a sampling circuit wherein first and second data are sampled onto different paths following the first (rising) edge and second (falling) edge of a signal (Yoon, ¶[0045]) and further output in response to the same command edge of the clock signal (Yoon, ¶[0046]). A person having ordinary skill in the art, before the effective filing date of this application, would have been able to combine the dual-data path structure of Chae with the synchronized outputs of Yoon, with a reasonable expectation of success. The underlying sampling, delay, and shared-clock techniques were already present in both inventions and well known in conventional memory interface design. The combination of known prior art elements according to known methods to yield predictable results is obvious and not patentable.
Regarding Claim 2, Chae discloses the command sampling circuit according to claim 1, wherein
the delay circuit comprises an even number of inverters.
Delay chains in memory interface circuits are routinely implemented using inverters or inverter pairs, the latter being more common as it results in a non-inverted delay preserving the original polarity of the signal. Regardless of this benefit, there are only two options for an inverter chain, an even number of inverters or an odd number of inverters. A limitation may be considered obvious to try if there are a finite number of identified predictable solutions with a reasonable expectation of success (See KSR, 550 U.S. at 418, 82 USPQ2d at 1396). Therefore, implementing the circuit of Claim 1 with a delay circuit comprising an even number of inverters is obvious and not patentable.
Regarding Claim 3, Yoon discloses the command sampling circuit according to claim 1, wherein
the output edge of the output clock is located at the second sampling edge (The designation of first or second data sampling edge is arbitrary as either the rising or falling edge, or other transition, may be designed the first or second edge. Disclosing outputting first and second data in response to the same clock signal: Yoon, ¶[0046]), or
is located after the second sampling edge and has a preset delay amount relative to the second sampling edge, the delay amount satisfying a timing requirement required for sampling at the output edge (Sampling first and/or second data in accordance with a delayed signal: Chae, col.13:29-35).
Regarding Claim 4, Chae discloses the command sampling circuit according to claim 3, wherein
the sampling circuit (Sampling circuit including a flip-flop: Chae, col.6:39-40) and the command decoding circuit both comprise a flip-flop (The decoding circuit including a latch: Chae, col.5:52-53);
the delay amount comprises a setup time of a flip-flop in the command decoding circuit and a hold time of a flip-flop in the sampling circuit (Sampled data being latched at a center or ¼ point of the data signal, inherently requiring accounting for setup time and hold time of related latches: Yoon, ¶[0018]).
Regarding Claim 5, Yoon discloses the command sampling circuit according to claim 3, wherein
the delay amount is not greater than a difference between a time that elapsed between the first sampling edge and the second sampling edge and the setup time of the flip-flop in the command decoding circuit (Sampled data being latched at a center or ¼ point of the data signal, inherently requiring accounting for sampling edges and the setup time of the related latches: Yoon, ¶[0018]).
Regarding Claim 6, Chae discloses the command sampling circuit according to claim 1, wherein
the sampling clock comprises an odd clock and an even clock (The sampling clock having an odd and an even clock cycle: Chae, Figure 4);
the sampling circuit comprises a first sampling sub-circuit and a second sampling sub-circuit (The sampling circuit first and second sub-circuits: Yoon, ¶[0011]),
the first sampling sub-circuit having a first even output end and a second even output end (Outputting the first and second data streams: Yoon, ¶[0012]),
the second sampling sub-circuit having a first odd output end and a second odd output end (Outputting the third and fourth data streams: Yoon, ¶[0012]);
an input end of the first sampling sub-circuit is connected to an input end of the second sampling sub-circuit for receiving the memory command (First and second sampling sub-circuits connected for receiving a joint signal: Yoon, ¶[0011]);
a clock end of the first sampling sub-circuit receives the even clock, and a clock end of the second sampling sub-circuit receives the odd clock (Sampling circuits controlled by respective signals: Yoon, ¶[0010]);
the delay circuit comprises a first delay sub-circuit and a second delay sub-circuit (The sampling circuit first and second sub-circuits: Yoon, ¶[0011]),
the first even output end being connected to an input end of the first delay sub-circuit (The first output being connected to the first delay sub-circuit: Chae, col.5:17-25), and
the first odd output end being connected to an input end of the second delay sub-circuit (The second output being connected to the second delay sub-circuit: Chae, col.5:17-25);
output ends of the first delay sub-circuit and the second delay sub-circuit, and the second even output end and the second odd output end
are all connected to the command decoding circuit (Delay sub-circuits connected to the output circuits: Chae, Figure 2);
the second even output end and the second odd output end are connected to the address output circuit (Data outputs connected to the second FIFO circuit: Chae, Figure 2).
Regarding Claim 7, Chae discloses the command sampling circuit according to claim 6, wherein
the command decoding circuit comprises a decoding circuit and a decoding output circuit (FIFO circuit comprising registers, divider, multiplexers, and signal generator: Chae, col.13:23-28);
an input end of the decoding circuit is connected to the output ends of the first delay sub-circuit and the second delay sub-circuit (Decoding circuit connected to first and second delay circuits: Chae, Figure 2), and
the second even output end and the second odd output end, an output end of the decoding circuit is connected to the decoding output circuit (Sampler outputs connected to decoding circuits: Chae, Figure 2), and the decoding circuit is configured to perform decoding processing (Decoding circuit inherently configured to perform decoding processing by definition);
the decoding output circuit receives the output clock and is configured to output, in response to the output edge, a decoded result currently output by the decoding circuit as the decoding information of the memory command (The FIFO circuit receiving clock signal: Chae, Figure 2; And configured to output decoded data: Chae, col.6:14-17).
Regarding Claim 9, Chae discloses the command sampling circuit according to claim 6, wherein
an input end of the address output circuit is connected to the second even output and the second odd output (Second FIFO circuit connected to second output: Chae, Figure 2),
a clock end of the address output circuit receives the output clock (Second FIFO circuit receiving a clock signal: Chae, Figure 2), and
the address output circuit is configured to output, in response to the output edge, a current output of the second even output end or the second odd output end as the address information of the memory command (The FIFO circuit receiving clock signal: Chae, Figure 2; And configured to output decoded data: Chae, col.6:14-17).
Regarding Claim 10, Chae discloses the command sampling circuit according to claim 9, wherein
the address output circuit comprises a first output circuit, a second output circuit, and an integration circuit (Second FIFO circuit Outputting dual outputs and integrated with third FIFO circuit: Chae, Figure 12);
an input end of the first output circuit is connected to the second even output end, a clock end of the first output circuit receives the output clock, and the first output circuit is configured to output, in response to the output edge, the current output of the second even output end (First FIFO circuit configured to output data signal in response to input data signal and delayed clock signal: Chae, Figure 12);
an input end of the second output circuit is connected to the second odd output end, a clock end of the second output circuit receives the output clock, and the second output circuit is configured to output, in response to the output edge, the current output of the second odd output end (Second FIFO circuit configured to output data signal in response to input data signal and delayed clock signal: Chae, Figure 12);
the integration circuit is coupled to the first output circuit and the second output circuit, and is configured to integrate the outputs of the first output circuit and the second output circuit and output an integrated output as the address information of the memory command (Third FIFO circuit configured to integrate first and second signals and output a read data stream: Chae, Figure 12).
Regarding Claim 11, Chae discloses the command sampling circuit according to claim 1, further comprising:
a clock generation circuit (Sampling circuit configured to adapt the input clock signal: Chae, col.5:26-41),
wherein the clock generation circuit receives the sampling clock (Sampling circuit receiving the clock signal: Chae, Figure 2),
is coupled to the command decoding circuit and the address output circuit (Sampling circuit connected to first FIFO circuit: Chae, Figure 2), and
is configured to generate the output clock according to the sampling clock (Sampling circuit outputting clock signal: Chae, Figure 2, as amended above).
Regarding Claim 12, Chae discloses a memory, comprising:
the command sampling circuit, the command decoding circuit, and the address output circuit according to claim 1 (The circuits configured to work in a memory device: Chae, col.1:15-17).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,857,973 B1 to Kwanyeob Chae, et al. (hereafter Chae) and US 20050157827 A1 to Yong-Jin Yoon, et al. (hereafter Yoon) further in view of US 20240290365 A1 to Youngkwon Jo (hereafter Jo).
Regarding Claim 8, Chae discloses the command sampling circuit according to claim 7, wherein
an input end of the first decoding circuit is connected to the second even output end and the second odd output end (First FIFO circuit connected to the sampling output and clock signal: Chae, Figure 2),
an output end of the first decoding circuit is connected to the decoding output circuit (First FIFO circuit connected to second FIFO circuit: Chae, Figure 2), and
the first decoding circuit is configured to decode a received command and output a corresponding decoded result (First FIFO circuit configured to decode received input data and output decoded signal: Chae, col.5:26-41);
an input end of the second decoding circuit is connected to the output ends of the first delay sub-circuit and the second delay sub-circuit (Second FIFO circuit receiving data stream and delayed clock signal: Chae, Figure 2),
an output end of the second decoding circuit is connected to the decoding output circuit (Output of the decoding circuit is output: Chae: Figure 2), and
the second decoding circuit is configured to decode a received command and output a corresponding decoded result (Second FIFO circuit configured to decode received input data and output decoded signal: Chae, col.6:9-13);
the decoding output circuit receives the output clock and outputs, in response to the output edge, a decoded result currently output by the first decoding circuit or the second decoding circuit as the decoding information of the memory command (Output circuit outputting synchronized output in response to clock signal: Yoon, ¶[0046]).
Chae and Yoon disclose the sampler structure described in Claim 8, but do not disclose using it in either a 1N or 2N mode. Jo, however, discloses a similar sampler structure wherein:
the decoding circuit comprises a first decoding circuit corresponding to a 1N mode and a second decoding circuit corresponding to a 2N mode (Command decoder 32 configured to decode 1N or 2N mode: Jo, ¶[0031]);
Jo discloses this allows the decoding unit to work in either a 1N configuration (The 1N mode reduces command execution latency) or a 2N configuration (The 2N mode provides a wider command address capture window). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the flexible configurations of Jo with the sampling structure of Chae, with a reasonable expectation of success. Both inventions are well known in the field of data command sampling circuits and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2025/0239295 A1 to Yanpeng Xie and Zequn Huang: Disclosing a similar sampling circuit configured to output control signals according to a sampling signal and command address.
US 12,387,770 B2 to Zequn Huang: Disclosing a similar sampling circuit configured to output control signals according to a sampling signal and command address.
US 12,374,384 B2 to Zequn Huang: Disclosing a similar sampling circuit configured to output control signals according to a sampling signal and command address.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/JEROME LEBOEUF/ Primary Examiner, Art Unit 2824 - 07/14/2026
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