DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Based on the amendments to the claims, the previous restriction requirement has been withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/4/24 has been considered by the examiner.
Claim Objections
Claims 1, 9, and 17 are objected to because of the following informalities: the first use of the acronym 3D PHY should be defined. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3-9 and 11-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akel et al. US 2024/0088084 in view of Park et al. US 2022/0113889
As per claim 1, Akel et al. apparatus, comprising: one or more memory dies (figure 1 element 102); and an interface die comprising (figure 1 element 112): a 3D (stacked memory, figure 1 element 104) PHY (figure 1 element 112) communicatively coupled to the one or more memory dies via Through-Wafer Interconnects (TWIs) (paragraph [0021] through silicon via), wherein the 3D PHY is configured to communicate with a host device via a customized communication interface (Paragraph [0016]); and a memory built-in self-test (MBIST) circuit communicatively coupled to the one or more memory dies via the TWIs (Paragraph [0019], Fig 7).
Not explicitly taught by Akel et al. is that the self-test is a MBIST as claimed. However, in an analogous art Park et al teaches a memory built-in self-test (Abstract) in the context of stacked memory circuitry. Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to use a memory built in self-test to test stacked memory dies as suggested om the abstract of Akel et al.
Claim 9, directed to the interface die, is substantially the same as claim 1 and is rejected for the same reasoning as claim 1.
As per claims 3 and 11, Park et al. teaches the MBIST circuit comprises test patterns of data and instructions for performing a test of the apparatus (Paragraph [0135]).
As per claims 4 and 12, Park et al. teaches the MBIST circuit is configured to output a test result of the one or more memory dies to an external device (paragraphs [0130-0131]).
As per claims 5 and 13 Akel et al teach each of the one or more memory dies comprises respective interface circuitry to communicate with the interface die via the TWIs (TSV Figure 6 element 624 paragraphs [0025-0027]).
As per claims 6 and 14, Park et al. teaches the MBIST circuit is configured to communicate with the respective interface circuitry of the one or more memory dies via the TWIs (Paragraphs [0134-0135] Fig 12).
As per claims 7 and 15 Park et al. teaches the MBIST circuit is configured to select a memory die of the one or more memory dies for testing by sending a select signal (control signals) via the TWIs to the respective interface circuitry (Paragraph [00134]).
As per claim 16 Park et al teaches the 3D PHY is communicatively coupled (Paragraph [0037]) to the host device via a plurality of micro-bumps, and wherein the host device comprises the customized communication interface (paragraph [0134]).
As per claim 8, Park et al. teaches memory dies form a three-dimensional (3D) high bandwidth memory (HBM) cube (Paragraph [0133])
Allowable Subject Matter
Claims 2 and 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowable over the prior arts of record.
The following is a statement of reasons for the indication of allowable subject matter: The “claimed invention of independent claim 17 recites:
“A memory device, comprising:
a memory built-in self-test (MBIST) circuit of a memory device, comprising:
an address generator communicatively coupled to one or more memory dies of the memory device via Through-Wafer Interconnects (TWIs), wherein the address generator is configured to generate address data and transmit the address data to the one or more memory dies via the TWIs;
a data generator communicatively coupled to the one or more memory dies of the memory device via the TWIs, wherein the data generator is configured to generate input data and transmit the input data to the one or more memory dies via the TWIs;
a comparator communicatively coupled to the one or more memory dies of the memory device via the TWIs, wherein the comparator is configured to receive output data from the one or more memory dies via the TWIs and analyze the output data; and
a built-in self-test (BIST) controller communicatively coupled to the one or more memory dies of the memory device via the TWIs, wherein the BIST controller is communicatively coupled to the address generator, the data generator, and the comparator; and a
3D PHY communicatively coupled to the one or more memory dies of the memory device via the TWIs, wherein the 3D PHY is configured to communicate with a host device via a customized communication interface, and wherein the MBIST is configured to communicate, via the TWIs, data with the 3D PHY of the memory device.”
The prior arts of record teach
US 2025/0201722 to Loh et al. teaches a 3D chip stack connected to a separate chip via an elevated fanout bridge. The apparatus can be configured to deliver power to an interposer die without obstruction. Instead of blocking any part of the power delivery to the interposer die, through-silicon vias can be placed in the edge of the interposer die, and additional through-silicon vias can be placed in a dummy die on top of the elevated fanout bridge. A backside bridge can transmit signals from the physical interfaces of the interposer die to the elevated fanout bridge through the two sets of through-silicon vias.
US 20250103488 to Kang et al. teaches a stacked semiconductor memory, an application specific integrated circuit (ASIC) die, and an interposer. The stacked semiconductor memory and the ASIC die may be connected to the top of the interposer. The stacked semiconductor memory may correspond to an HBM with a bandwidth increased by stacking a plurality of memory chips, e.g., a plurality of dies, and electrically connecting the plurality of memory chips to each other via a TSV base die may include a PHY interface, an HBM controller, a low latency channel (LLC), a UCI port, a boot module, and a test module.
However, the prior arts of record fail to teach the claimed specifics of independent claim 17. As such, modification of the prior arts of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior arts. Therefore, it is not clear that one of ordinary skill in the art at the time of the invention would have made the necessary modifications to the prior arts of record to encompass the limitations set forth in the present claims. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate or render obvious the combined specifics of the claimed invention. Hence, claims 17-20 are allowable over the prior arts of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/ Primary Examiner, Art Unit 2111
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