DETAILED ACTION
This Final action is responsive to communications: 08/10/2026.
Applicant amended claims 1, 11, 15, 18, and 20; no claims are cancelled or none added. Claims 1-20 are pending. Claims 1, 11, and 18 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, undue breadth of the claim may be addressed under different statutory provisions, depending on the reasons for concluding that the claim is too broad. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 08/10/2026. Part of IDS has been considered. (See strike through reference portion not considered since prior art inventor does not match with reference).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claim 1-2 is/are rejected under 35 U.S.C. 103 as being obvious over Xu et al. (US 2008/0117660 A1) , in view of BAE et al. (US 2014/0241043 A1).
Regarding independent claim 1, Xu teaches a memory device (para [0020], Fig. 2 “one-time programmable memory device” employed with Fig. 4: 170 “anti-fuse cell” structure. See Examiner’s Markup version of Xu Figure 4),
comprising a one-time programmable non-volatile memory OTP NVM cell (Fig. 4: 170) that comprises:
PNG
media_image1.png
562
658
media_image1.png
Greyscale
an antifuse element (Fig. 4: 80 “anti-fuse element”, see para [0024]) having a first terminal (Fig. 4: A) coupled to a program line (Fig. 4: line 135 coupled to Vpp);
a first transistor (Fig. 4: 100) coupled between a second terminal of the antifuse element (Fig. 4: B) and a source line (Fig. 4: column 1 data transfer line. See Fig. 4: SL1, BL1 is connected to column 1 data transfer line),
wherein the first transistor (Fig. 4: 100) is configured to be turned on to form a write path to the antifuse element (para [0025]: “…transistor 100 is controlled at its gate by a signal on word line WL1 to select a row which is accessed along with a selected column and associated bit line BL1 during memory cell… programming…”);
a second transistor (Fig. 4: 120), wherein a control terminal of the second transistor (Fig. 4: gate of 120) is coupled to the second terminal of the antifuse element (Fig. 4: 130); and
a third transistor (Fig. 4: 110) configured to be turned on to form a read path to the antifuse element (para [0027]: “…couples amplifying transistor 120 to a column line, e.g., Vout1… transistor 110 has a gate controlled by a signal on word read line WR1…”),
wherein a first terminal of the third transistor (Fig. 4: C) is coupled to the source line (Fig. 4: column 1 data transfer line. See Fig. 4: SL1, BL1 is connected to column 1 data transfer line) and
a second terminal of the third transistor (Fig. 4: D of 110) is coupled to a first terminal of the second transistor (Fig. 4: D of 120),
wherein a first terminal of the first transistor (Fig. 4: upper BL1 terminal of 100) and the first terminal of the third transistor (Fig. 4: C) are coupled together to the source line (Fig. 4: column 1 data transfer line. See Fig. 4: SL1, BL1 is connected to column 1 data transfer line).
Xu is silent with respect to column specific data transfer line i.e. Xu is silent with respect to SL, and BL lines connected to column specific data transfer line.
BAE teaches SL, and BL lines per column are commonly connected to respective column specific data transfer line (Fig. 4: column “data transfer line” data<0> is connected to SL0, BL0. See para [0090]).
Xu and BAE are in the same field of endeavor of resistive memory operation and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of BAE into the apparatus of Xu such that column specific data transfer line can be employed in the construction of memory device in order to enable memory column repair scheme and thus reduce manufacturing cost.
Regarding claim 2, Xu and BAE teach the memory device of claim 1. Xu teaches wherein a control terminal of the first transistor (Fig. 4: gate of 100) is coupled to a write word line (Fig. 4: WL1 “word line”, para [0025]: used for programming),
a second terminal of the second transistor is coupled to a bit line (Fig. 4: upper Vdd terminal of 120 is operably coupled to SL1 and BL1) and a control terminal of the third transistor (Fig. 4: gate of 110) is coupled to a read word line (Fig. 4: WR1, para [0027: “word read line”),
wherein in a write operation (Fig. 5: during programming, see t-program), the write word line and the program line have a first voltage (Fig. 5 and Fig. 4: VWL and VPP are kept at “high level”), and the read word line (during t-program WR1 is not active and kept at “low level”) and the bit line have a ground voltage (Fig. 5: BL is kept at “low level” during t-program).
10. Claim 11 is/are rejected under 35 U.S.C. 103 as being obvious over Wu et al. (US 2016/0104542 A1), in view of BAE et al. (US 2014/0241043 A1).
Regarding independent claim 11, Wu teaches an integrated circuit (memory device with Fig. 2: 200 memory cell. See Figure 3 x-sectional structure of memory cell. See Examiner’s Mark-up of Wu Figure 3), comprising:
PNG
media_image2.png
617
900
media_image2.png
Greyscale
a first transistor (Fig. 3: 210 “transistor”. See also Fig. 2) comprising a first gate structure extending along a first direction (Fig. 3: G1 extends in y-direction into page plane);
a second transistor (Fig. 3: 220 “transistor”. See also Fig. 2) comprising a first active area (Fig. 3: S2, D2 area viewed from z-direction) coupled to a source line (Fig. 2: drain/ source of 220 is operably coupled to source line Fig. 2: SL) and
a second active area (Fig. 3: E2 area viewed from z-direction) separated from the first active area (Fig. 3: S2, D2) along a second direction (Fig. 3: x-direction); and
an antifuse element (Fig. 3: 230. See also Fig. 2: 230) comprising a third active area (Fig. 3: S3, D3 area viewed from z-direction) and a fourth active area (Fig. 3: E3 area viewed from z-direction) connected to the third active area (Fig. 3: S3, D3 area),
wherein the third active area and the fourth active area have different conductive types (in context of para [0024], Fig. 3: E3 is “source/ drain extension area” and is fabricated with low doped material unlike source/ drain. Thus, their conductivity type is not the same) and are coupled to the second active area (Fig. 3: E2 area) and the first gate structure (Fig. 3: G1) through a conductive segment (Fig. 3: coupled via p well or p substrate);
a third transistor comprising a fifth active area (Fig. 2: 240 and associated active region), wherein the first active area (Fig. 3: S2, D2 coupled to BL of column data transfer line. See Fig. 1 or Fig. 6 for column structure) and the fifth active area are coupled together to the source line (Fig. 2: 240 coupled to SL of column data transfer line. See Fig. 1 or Fig. 6 for column structure).
Wu is silent with respect to column specific data transfer line i.e. Wu is silent with respect to SL, and BL lines connected to column specific data transfer line.
BAE teaches SL, and BL lines per column are commonly connected to respective column specific data transfer line (Fig. 4: column “data transfer line” data<0> is connected to SL0, BL0. See para [0090]).
Wu and BAE are in the same field of endeavor of resistive memory operation and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of BAE into the apparatus of Wu such that column specific data transfer line can be employed in the construction of memory device in order to enable memory column repair scheme and thus reduce manufacturing cost.
11. Claim 12 is/are rejected under 35 U.S.C. 103 as being obvious over Wu et al. (US 2016/0104542 A1) and BAE et al. (US 2014/0241043 A1), in view of Wu-7730 (US 2015/0287730 A1).
Regarding claim 12, Wu and BAE teach the integrated circuit of claim 11. They are silent with respect to remaining provisions of this claim as it pertains to well structures used to build antifuse and access circuitry.
Wu-7730 teaches a first well having a first conductive type, wherein the first transistor is arranged on the first well (Fig. 2A, Fig. 2B: 204 well is used for access transistor 234); and
a second well that is next to the first well along the first direction and has a second conductive type different from the first conductive type (Fig. 2A, Fig. 2B: 236 is used for antifuse 232), wherein the antifuse element is arranged on the second well (Fig. 2A, Fig. 2B in context of para [0096]: antifuse and access transistors are fabricated in well of different conductivity type).
An ordinary skill in the art would understand the use of Wu-7730’s fabrication method into the apparatus of Wu and BAE.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teachings of Wu-7730 into the apparatus of Wu and BAE such that two different well can be employed in the device to construct antifuse and access transistors in order to reduce device leakage.
Response to Arguments
Based on Title amendment, previous title objections are withdrawn.
Applicant’s arguments with respect to claim(s) 1, and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 18-20 are indicated as allowable.
Claims 3-10, and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
PENG (US 2013/0208525 A1): Fig. 1A-Fig 9 disclosure applicable for all claims.
KIM (US 2013/0077376 A1): Fig. 1-Fig. 9 disclosure applicable for all claims.
Yanagisawa (US 2015/0103579 A1): Yanagisawa teaches a one-time programmable (OTP) memory cell (Fig. 8C: 4 “memory cell”. See para [0166]. See also, Fig. 3A cell) comprising: a main OTP cell transistor (Fig. 8C: 20b “memory element”), a redundant OTP cell transistor (Fig. 8C: 20a “memory element”), and an access transistor (Fig. 8C: 10 “selection transistor”) connected in series (See Fig. 8C) between a first node (Fig. 8C: tm) and a second node (Fig. 8C: ts), the first node being in a floating state, the OTP memory cell is configured to apply a program voltage (applying voltage to “writing targets” to both 20a, 20b and forming “filament” resistance as shown in Fig. 10: STATE3. See also, para [0180], para [0183] and Fig. 9C).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
Prosecution Insights