DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-8, 10, 13, 15-16 and 18-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scott et al. (USPN 10,447,344)
With respect to claim 2, a field effect transistor (FET) switch stack (Fig. 10, wherein Scott et al. anticipates that the circuit of Fig. 10 is connected in a “stack”, i.e., “more than one transistor” and “more than one transistor in the stack”, see Col. 15 lines 26-29. Furthermore, see Figs. 2B and 3A) comprising:
serially connected FETs (F of Fig. 10, Scott et al. anticipates more than one transistor of a stack of multiple transistors of Fig. 10, see “more than one transistor” and “more than one transistor in the stack”, see Col. 15 lines 26-29. Furthermore, see Figs. 2B and 3A) coupled at one end to a first terminal (S terminal of the first transistor of the stack) and at another end to a second terminal (D terminal of the last transistor of the stack), the first terminal being configured to receive a radio frequency (RF) signal (signal on S, Fig. 10 is an RF switch and thus receives RF signals at the input);
a body resistor ladder (RGB1 and RGB2 and/or each RGB1 and RGB2 for each body of each transistor in the anticipated more than one transistor stack of Fig. 10) comprising a plurality of body resistor elements connected in series (RGB1, RGB2 and/or each RGB1 and each RGB2 of each of the multiple transistors of the anticipated transistor stack of Fig. 10), each body resistor element coupled across body terminals of corresponding adjacent FETs of the serially connected FETs (each RGB1 and RB2 of each anticipated multiple transistor stack of Fig. 10 are serially connected across the body terminal of each switch) and;
a first diode stack (at two diodes of at least one of DBS2#, DBSB1#, DDB1# and DDB2#) comprising at least two diodes connected in series (each stack includes at least two serially connected diodes) and coupled between a first tapping point of the body resistor ladder (terminal between RGB1 and RBG2) and the first terminal (DBS2# and DBSB1# are directly connected to S, DDB1# and DDB2# connected to S via DBS2# and DBSB1# ); and
a bias voltage generator (RSD, VR1, DF2, CB, DF1, VR2, RB1 and RB2) configured to dynamically adjust bias voltage across the body resistor ladder (the circuit adjusts the body voltage) based on the RF signal characteristics (the body voltage is adjusted, e.g., boosted positive or negative, responsive to the RF signal, see Col. 13 lines 25-37), to ensure uniform voltage distribution across the switch stack (uniform distribution of VDS, i.e., NxVDS, see Col. 15 lines 29-32 and to provide charge balance, see Col. 13 lines 21-23 and thus uniform distribution).
With respect to claim 3, the FET switch stack of claim 2, wherein the first diode stack is configured to provide a first gate-induced drain leakage (GIDL) current discharge path during an OFF state of the FET switch stack (discharge provided by DBS2#, DBSB1#, see Col. 14 lines 50-52).
With respect to claim 4, the FET switch stack of claim 3, wherein the bias voltage generator comprises a control circuit configured to adjust the bias voltage to reduce the GIDL current (when the switch is OFF the bias voltage generator generates a negative voltage, see Col. 7 line 65 to Col. 8 line 1 and Col. 13 lines 25-32. A negative voltage on the body voltage of an NMOS transistor, such as F of Fig. 10, will reverse bias the NMOS transistor thus reducing leakage current).
With respect to claim 5, the FET switch stack of claim 4, wherein the bias voltage generator generates a negative bias voltage during the OFF state of the switch stack (when the switch is OFF the bias voltage generator generates a negative voltage, see Col. 7 line 65 to Col. 8 line 1 and Col. 13 lines 25-32)
With respect to claim 7, the FET switch stack of claim 2, further comprising a first diode element arrangement (e.g., DSB2# with DSB1#; alternatively DSB2# with DSB1# of the first transistor of the stack and DSB1# with DSB2# of subsequent transistor of the stack) coupled to a first tapping point of the body resistor ladder (body terminal connected to RBG1), the first diode element arrangement comprising the first diode stack (e.g., DSB2#; alternatively DSB2# with DSB1# of the first transistor of the stack) and at least one additional component selected from a resistor, capacitor, or secondary diode stack (e.g., DSB1#; DSB1# with DSB2# of subsequent transistor of the stack).
With respect to claim 8, the FET switch stack of claim 7, wherein the first diode element arrangement and a second diode element arrangement are coupled to distinct tapping points of the body resistor ladder (DSB1# with DSB2# of subsequent transistor of the stack is coupled to a distinct tapping point within the subsequent transistor).
With respect to claim 10, the FET switch stack of claim 2, wherein the body resistor ladder is configured to distribute voltage proportionally across the FETs based on their relative positions in the stack (the voltage is distributed evenly equal to NxVDS and thus is based on the relative serial position).
With respect to claim 13, the FET switch stack of claim 2, wherein the body resistor ladder includes resistors configured to split into two or more series resistors (RBG1 and RGB2), with the common points of connection serving as tapping points (at the body terminal/voltage).
With respect to claim 15, the FET switch stack of claim 2, wherein the bias voltage generator is configured to adjust the bias voltage to maintain balanced voltage distribution across the FETs to prevent breakdown of transistors in the stack (by balancing the charge and voltage across each transistor the breakdown of the FETs will be prevented).
With respect to claim 16, the FET switch stack of claim 2, wherein the first terminal is configured to receive an RF signal applied with a peak voltage distributed proportionally across the serially connected FETs (each RSD of the stacked transistor will proportionally distribute the voltage on S across all of the transistors of the stack).
With respect to claim 18, a method of managing gate-induced drain leakage (GIDL) current (method of operating Fig. 10) in a field effect transistor (FET) switch stack (Fig. 10, wherein Scott et al. anticipates that the circuit of Fig. 10 is connected in a “stack”, i.e., “more than one transistor” and “more than one transistor in the stack”, see Col. 15 lines 26-29. Furthermore, see Figs. 2B and 3A), the method comprising:
applying a radio frequency (RF) signal to a first terminal of the FET switch stack (RF signal at S terminal);
dynamically adjusting bias voltage across a body resistor ladder to distribute voltage evenly across serially connected FETs (RSD, VR1, DF2, CB, DF1, VR2, RB1 and RB2 dynamically adjusts the body voltage. The body voltage is adjusted, e.g., boosted positive or negative, responsive to the RF signal, see Col. 13 lines 25-37), to ensure uniform voltage distribution across the switch stack (uniform distribution of VDS, i.e., NxVDS, see Col. 15 lines 29-32 and to provide charge balance, see Col. 13 lines 21-23 and thus uniform distribution); and
generating multiple GIDL current discharge paths through at least two diode element arrangements during different intervals of an RF signal swing (discharge paths of DSB2# with DSB1# and SDB1# with SDB2# which are provided during different swing intervals when S is larger than the combined threshold of DSB2# with DSB1# and when D is larger than the combined threshold of SDB1# with SDB2#).
With respect to claim 19, the method of claim 18, wherein the bias voltage adjustment prevents breakdown of transistors in the FET switch stack (by balancing the charge and voltage across each transistor the breakdown of the FETs will be prevented).
With respect to claim 20, the method of claim 18, wherein the GIDL current discharge paths are configured to partially overlap during RF signal transitions (overlap set by threshold voltage of the diode strings).
With respect to claim 21, the method of claim 18, further comprising generating discharge paths through at least one tapping point of the body resistor ladder (body terminal connected to resistor ladder RGB1 and RGB2).
Allowable Subject Matter
Claims 6, 9, 11-12, 14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849