Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 2, 12 and 16
b. Pending: 2-21
Claim 1 has been canceled and claims 2-21 have been newly added through preliminary amendments.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 1/17/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. US 12154639. Although the claims at issue are not identical, they are not patentably distinct from each other because when we compare independent method claim 2 of Instant Application with independent method claim 1 of USP’639, we find that they both recite the same claim limitations. Same observation is true for all dependent claims and independent device claim 12 (16) of Instant Application vs. independent device claim 13 (18) of USP’639. Please see the below table.
Instant Application
USP 12154639
2. A method, comprising: receiving a configuration for a memory device, the configuration corresponding to a circuit node of the memory device; coupling the circuit node to a first resistor of a set of resistors based at least in part on a fault condition associated with the memory device; and biasing the circuit node of the memory device to a first voltage value based at least in part on coupling the circuit node to the first resistor.
1. A method, comprising: receiving a configuration for a memory device, the configuration corresponding to a circuit node of the memory device, the circuit node selectively coupled with a set of resistors associated with the memory device; coupling the circuit node to a first resistor of the set of resistors based at least in part on a fault condition associated with the memory device; and biasing the circuit node of the memory device to a first voltage value satisfying a first voltage threshold based at least in part on coupling the circuit node to the first resistor.
12. A memory system, comprising: a circuit comprising a set of resistors; and processing circuitry operable to cause the memory system to: receive a configuration for a memory device of the memory system, the configuration corresponding to a circuit node of the circuit; couple the circuit node to a first resistor of the set of resistors based at least in part on a fault condition associated with the memory device; and bias the circuit node of the memory device to a first voltage value based at least in part on coupling the circuit node to the first resistor.
13. A memory system, comprising: a circuit comprising a set of resistors; a switch operable to couple one or more resistors of the set of resistors to a circuit node; and processing circuitry operable to cause the memory system to: receive a configuration for a memory device of the memory system, the configuration corresponding to the circuit node of the circuit; couple the circuit node to a first resistor of the set of resistors based at least in part on detecting a fault condition associated with the memory device; and bias the circuit node of the circuit to a first voltage value based at least in part on the coupling, the first voltage value satisfying a first voltage threshold.
16. A memory system, comprising: one or more memory devices; and processing circuitry configured to couple with the one or more memory devices and configured to cause the memory system to: receive a configuration for a memory device of the one or more memory devices, the configuration corresponding to a circuit node of the memory device; couple the circuit node to a first resistor of a set of resistors based at least in part on detecting a fault condition associated with the memory device; and bias the circuit node of the memory device to a first voltage value based at least in part on coupling the circuit node to the first resistor, the first voltage value.
18. A memory system, comprising: one or more memory devices; and processing circuitry configured to couple with the one or more memory devices and configured to cause the memory system to: receive a configuration for a memory device of the one or more memory devices, the configuration corresponding to a circuit node of the memory device, the circuit node selectively coupled with a set of resistors associated with the memory device; couple the circuit node to a first resistor of the set of resistors based at least in part on detecting a fault condition associated with the memory device; and bias the circuit node of the memory device to a first voltage value satisfying a first voltage threshold based at least in part on coupling the circuit node to the first resistor, the first voltage value.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kasnavi et al. (US 7620853)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 6/30/2026
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