Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7,12, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Alsop (Patent Application Publication 2021/0389907) in view of Natu (Patent Application Publication 2018/0165100).
Claim 1. Alsop teaches transmitting an activation command to open a set of rows of a memory device, each row of the set of rows corresponding to a set of memory cells at the memory device; transmitting a write command after transmitting the activation command, the write command indicating a same logic state is to be stored in a respective memory cell of each row of the set of rows (coalesced row activation and write command for multiple rows or banks Fig 3, 5-7 Aslop [0026-0030, 0038-0046]).
Natu teaches a write command indication that the same logic state, such as zeros, is to be stored in memory cells for the purpose of initializing memory by writing known data values (write only initialization by writing zeroes to memory Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Since Alsop and Natu are both from the same field of endeavor (memory commands) the purpose disclosed by Natu would have been recognized in the pertinent are of Alsop.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the write command taught by Natu which indicates the same logic state is to be stored in a respective memory cell of each row of the set of rows in the circuit taught by Also for the purposes of initializing memory by writing known data values (Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Claim 2. The method of claim 1, wherein: the write command is transmitted a duration after transmitting the activation command; and the duration is different than a row address to column address delay (row-activate command before write command, Alsop Figs 5-7 [0038-0046]).
Claim 3. The method of claim 1, wherein the activation command is transmitted based at least in part on each row of the set of rows being coupled with a respective sense amplifier of a set of sense amplifiers (multiple rows or banks activated into row buffer structures, Alsop Fig 3 [0026-0030]).
Claim 4. The method of claim 1, wherein the respective memory cell of each row of the set of rows in which the same logic state is stored has a same column address (common column memory access across multiple rows or banks, Alsop Fig 5-7 [0033-0046]).
Claim 5. The method of claim 1, wherein: the activation command comprises one or more bits identifying the set of rows; and a respective row address of each row of the set of rows comprises the one or more bits (Command bits identify target memory locations for a coalesced command, Alsop Fig 4 [0031-0037]).
Claim 7. The method of claim 1, wherein: the write command indicates a column address (write command indication a common column address, Alsop Fig 5-7 [0033-0046]); and the same logic state is to be stored in the respective memory cell of each row of the set of rows based at least in part on the respective memory cell of each row being associated with the column address indicated via the write command (writing zeros to memory during initialization, Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Claim 8. Alsop teaches an apparatus comprising a controller associate with a memory device, wherein the controller is configured to cause the apparatus to transmit an activation command to open a set of rows of the memory device and transmit a write command after transmitting the activation command, but is silent with respect to the write command indicating a same logic state to be stored in a respective memory cell of each row of the set of rows (coalesced row activation and write command for multiple rows or banks Fig 3, 5-7 Aslop [0026-0030, 0038-0046]).
Natu teaches a write command indication that the same logic state, such as zeros, is to be stored in memory cells for the purpose of initializing memory by writing known data values (write only initialization by writing zeroes to memory Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Since Alsop and Natu are both from the same field of endeavor (memory commands) the purpose disclosed by Natu would have been recognized in the pertinent are of Alsop.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the write command taught by Natu which indicates the same logic state is to be stored in a respective memory cell of each row of the set of rows in the circuit taught by Also for the purposes of initializing memory by writing known data values (Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Claim 9. The apparatus of claim 8, wherein: the write command is transmitted a duration after transmitting the activation command; and the duration is different than a row address to column address delay (row-activate command before write command, Alsop Figs 5-7 [0038-0046]).
Claim 10. The apparatus of claim 8, wherein the activation command is transmitted based at least in part on each row of the set of rows being coupled with a respective sense amplifier of a set of sense amplifiers (multiple rows or banks activated into row buffer structures, Alsop Fig 3 [0026-0030]).
Claim 11. The apparatus of claim 8, wherein the respective memory cell of each row of the set of rows in which the same logic state is stored has a same column address (common column memory access across multiple rows or banks, Alsop Fig 5-7 [0033-0046]).
Claim 12. The apparatus of claim 8, wherein: the activation command comprises one or more bits identifying the set of rows; and a respective row address of each row of the set of rows comprises the one or more bits (Command bits identify target memory locations for a coalesced command, Alsop Fig 4 [0031-0037]).
Claim 14. The apparatus of claim 8, wherein: the write command indicates a column address (write command indication a common column address, Alsop Fig 5-7 [0033-0046]); and the same logic state is to be stored in the respective memory cell of each row of the set of rows based at least in part on the respective memory cell of each row being associated with the column address indicated via the write command (writing zeros to memory during initialization, Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Claim 15. Alsop teaches a non-transitory computer-readable medium storing code comprising instructions executable by one or more processors to transmit activation and write commands, but is silent with respect to the write command indicating a same logic state to be stored in a respective memory cell of each row of the set of rows (Control logic and instructions for memory command handling and coalesced commands Fig 3-7 Aslop [0026-0050]).
Natu teaches a write command indication that the same logic state, such as zeros, is to be stored in memory cells for the purpose of initializing memory by writing known data values (write only initialization by writing zeroes to memory Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Since Alsop and Natu are both from the same field of endeavor (memory commands) the purpose disclosed by Natu would have been recognized in the pertinent are of Alsop.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the write command taught by Natu which indicates the same logic state is to be stored in a respective memory cell of each row of the set of rows in the circuit taught by Also for the purposes of initializing memory by writing known data values (Natu Fig 3A-3D, 5A-5B, [0012-0015,0024-0027]).
Claim 16. The non-transitory computer-readable medium of claim 15, wherein: the write command is transmitted a duration after transmitting the activation command; and the duration is different than a row address to column address delay (row-activate command before write command, Alsop Figs 5-7 [0038-0046]).
Claim 17. The non-transitory computer-readable medium of claim 15, wherein the activation command is transmitted based at least in part on each row of the set of rows being coupled with a respective sense amplifier of a set of sense amplifiers (multiple rows or banks activated into row buffer structures, Alsop Fig 3 [0026-0030]).
Claim 18. The non-transitory computer-readable medium of claim 15, wherein the respective memory cell of each row of the set of rows in which the same logic state is stored has a same column address (common column memory access across multiple rows or banks, Alsop Fig 5-7 [0033-0046]).
Claim 19. The non-transitory computer-readable medium of claim 15, wherein: the activation command comprises one or more bits identifying the set of rows; and a respective row address of each row of the set of rows comprises the one or more bits (Command bits identify target memory locations for a coalesced command, Alsop Fig 4 [0031-0037]).
Claims 6, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Alsop (Patent Application Publication 2021/0389907) in view of Natu (Patent Application Publication 2018/0165100) further in view of Bains (Patent Application Publication 2016/0005457).
Claim 6, 13 , 20. Alsop and Nato teach the method of claim 1, apparatus of claim 8, and the device of claim 15 but are silent with respect to herein the one or more bits comprise one or more most significant bits (MSBs) of the respective row address of each row of the set of rows.
Bains teaches counter bits interpreted as MSB of the row address counter and causing every row having the same most significant bits to be selected, Bains Fig 1 [0021]
Since Alsop, Natu and Bains are from the same field of endeavor (memory commands) the purpose disclosed by Natu would have been recognized in the pertinent are of Alsop.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to modify the row identifying bits used in Alsop so that the bits comprise one or more MSB of the row address of each row of the set of rows in the circuit taught by Aslop and Natu for the purpose of identifying a group of rows without individually addressing every row (Bains [0021,0032]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/
Primary Examiner, Art Unit 2827
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