DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-10, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ke et al (US 2024/0395195 A1; Fig. 4) in view Ke et al (US 2024/0395195 A1; Fig. 5), and further in view of Amari (US 2015/0021572 A1).
Claim 1, Ke (Fig. 1-23) discloses a display device (01; Fig. 23; wherein discloses a display panel) comprising:
a plurality of first semiconductor transistors (M22 and M21; Fig. 4; wherein figure shows more than one transistor) having:
a first semiconductor layer (102; Fig. 8; wherein discloses a first semiconductor layer 102); and
each semiconductor pattern (M22 and M21; Fig. 4; wherein figure shows more than one transistor; m21; Fig. 8) of the first semiconductor transistors (M22 and M21; Fig. 4) located in the first semiconductor layer (102; Fig. 8); and
a second semiconductor transistor (M1; Fig. 4) having:
a second semiconductor layer (104; Fig. 8; wherein discloses a second semiconductor layer 104); and
each semiconductor pattern (m11; Fig. 8) of the second semiconductor transistors (M1; Fig. 4) located in the second semiconductor layer (104; Fig. 8; wherein discloses a second semiconductor layer) which is located on the first semiconductor layer (Fig. 8; wherein figure shows second semiconductor layer 104 formed on the first semiconductor layer 102; See Applicant’s figure 9 which shows the second semiconductor layer ACL2 “located on” the first semiconductor layer ACL1; therefore the Examiner believes Ke teaches the same layering shown in figure 8),
wherein a first electrode layer (107; Fig. 8; wherein discloses a metal layer) is located between the first semiconductor layer (102; Fig. 8) and the second semiconductor layer (104; Fig. 8),
a second electrode layer (106; Fig. 8; wherein discloses a third conductive layer 106) is located on the second semiconductor layer (104; Fig. 8),
a first transistor (M1; Fig. 4) among the second semiconductor transistors (M1; Fig. 4) includes a first semiconductor pattern (m11; Fig. 8) located in the second semiconductor layer (104; Fig. 8), a bridge pattern (L1; Fig. 8; Paragraph [0083]) located in the first electrode layer (107; Fig. 8), and an electrode pattern (M13; Fig. 8; Paragraph [0084]; wherein discloses a first electrode) located in the second electrode layer (106; Fig. 8), and
the electrode pattern (m13; Fig. 8) connects the first semiconductor pattern (m11/104; Fig. 8) and the bridge pattern (L1/107; Fig. 8).
Ke (Fig. 4) does not expressly disclose a plurality of second semiconductor transistors.
Ke (Fig. 5) discloses a plurality of second semiconductor transistors (Fig. 5; wherein figure further shows an embodiment in which the transistor M1 is changed to have multiple transistors (M11 and M12)).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke’s (Fig. 4) control module by applying a double transistor, as taught by Ke’s (Fig. 5), so to use a control module with a double transistor for improving the stability of the potential VN2 of the second node N2 (Paragraph [0071).
Ke does not expressly disclose the first semiconductor pattern includes an etched portion,
the electrode pattern passes through the etched portion of the first semiconductor pattern and contacts the bridge pattern.
Amari (Fig. 1A-20B) discloses the first semiconductor pattern (14; Fig. 1A; Paragraph [0065]; wherein discloses a semiconductor layer 14 which includes through-holes 14A and 14B) includes an etched portion (14A and 14B: Paragraph [0075]; wherein discloses “the through-holes 14A and 14B are formed by, for example, a photolithography process and an etching process in a manner of penetrating the channel protective film 15 and the semiconductor layer 14”),
the electrode pattern (16A; Fig. 2D) passes through the etched portion (14A; Fig. 1A and 2C) of the first semiconductor pattern (14; Fig. 1A and 2A-2D) and contacts the bridge pattern (Fig. 2D; wherein figure shows electrode 16A connected to conductive pattern below the semiconductor pattern).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke’s display device by applying a method of manufacturing the transistor, as taught by Amari, so to use a display device with a method of manufacturing the transistor for providing a thin film transistor that is reduced in contact resistance and improved in EM resistance, a method of manufacturing the thin film transistor, and an electronic apparatus (Paragraph [0007]).
Claim 9, Ke (Fig. 1-23) discloses a scan driver (010; Fig. 23) comprising a plurality of stages (100; Fig. 23) including a plurality of first semiconductor transistors (M21 and M22; Fig. 4; wherein figure shows more than one transistor) having:
a first semiconductor layer (102; Fig. 8; wherein discloses a first semiconductor layer 102); and
each semiconductor pattern (m21; Fig. 8) of the first semiconductor transistors (M21 and M22; Fig. 4) located in the first semiconductor layer (102; Fig. 8); and
a second semiconductor transistor (M1; Fig. 4) having:
a second semiconductor layer (104; Fig. 8; wherein discloses a second semiconductor layer); and
each semiconductor pattern (104; Fig. 8) of the second semiconductor transistors (M1; Fig. 4) located in the second semiconductor layer (104; Fig. 8; wherein discloses a second semiconductor layer) which is located on the first semiconductor layer (Fig. 8; wherein figure shows second semiconductor layer 104 formed on the first semiconductor layer 102),
wherein a first electrode layer (107; Fig. 8; wherein discloses a metal layer) is located between the first semiconductor layer (102; Fig. 8) and the second semiconductor layer (104; Fig. 8),
a second electrode layer (106; Fig. 8; wherein discloses a third conductive layer 106) is located on the second semiconductor layer (104; Fig. 8),
a first transistor (M1; Fig. 4) among the second semiconductor transistors (M1; Fig. 4) includes a first semiconductor pattern (m11; Fig. 8) located in the second semiconductor layer (104; Fig. 8), a bridge pattern (L1; Fig. 8; Paragraph [0083]) located in the first electrode layer (107; Fig. 8), and an electrode pattern (M13; Fig. 8; Paragraph [0084]; wherein discloses a first electrode) located in the second electrode layer (106; Fig. 8), and
the electrode pattern (m13; Fig. 8) connects the first semiconductor pattern (m11/104; Fig. 8) and the bridge pattern (L1/107; Fig. 8).
Ke (Fig. 4) does not expressly disclose a plurality of second semiconductor transistors.
Ke (Fig. 5) discloses a plurality of second semiconductor transistors (Fig. 5; wherein figure further shows an embodiment in which the transistor M1 is changed to have multiple transistors (M11 and M12)).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke’s (Fig. 4) control module by applying a double transistor, as taught by Ke’s (Fig. 5), so to use a control module with a double transistor for improving the stability of the potential VN2 of the second node N2 (Paragraph [0071).
Ke does not expressly disclose the first semiconductor pattern includes an etched portion,
the electrode pattern passes through the etched portion of the first semiconductor pattern and contacts the bridge pattern.
Amari (Fig. 1A-20B) discloses the first semiconductor pattern (14; Fig. 1A; Paragraph [0065]; wherein discloses a semiconductor layer 14 which includes through-holes 14A and 14B) includes an etched portion (14A and 14B: Paragraph [0075]; wherein discloses “the through-holes 14A and 14B are formed by, for example, a photolithography process and an etching process in a manner of penetrating the channel protective film 15 and the semiconductor layer 14”),
the electrode pattern (16A; Fig. 2D) passes through the etched portion (14A; Fig. 1A and 2C) of the first semiconductor pattern (14; Fig. 1A and 2A-2D) and contacts the bridge pattern (Fig. 2D; wherein figure shows electrode 16A connected to conductive pattern below the semiconductor pattern).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke’s display device by applying a method of manufacturing the transistor, as taught by Amari, so to use a display device with a method of manufacturing the transistor for providing a thin film transistor that is reduced in contact resistance and improved in EM resistance, a method of manufacturing the thin film transistor, and an electronic apparatus (Paragraph [0007]).
Claims 2 and 10, Amari (Fig. 1A-20B) discloses wherein the etched portion (14A or 14B; Fig. 1A; Paragraph [0075]) is a notch (14A and 14B; Fig. 7A, 24A and 24B; Fig. 7B; 34A and 34B; Fig. 7C) or an opening (14A, and 14B; Fig. 1A; 24A and 24B; Fig. 5A; 34A1-34A3 and 34B1-34B3; Fig. 6A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke’s display device by applying a method of manufacturing the transistor, as taught by Amari, so to use a display device with a method of manufacturing the transistor for providing a thin film transistor that is reduced in contact resistance and improved in EM resistance, a method of manufacturing the thin film transistor, and an electronic apparatus (Paragraph [0007]).
Claims 4 and 12, Amari (Fig. 1A-20B) discloses wherein the first semiconductor pattern (14; Fig. 1A) includes a first electrode (16A; Fig. 1B; wherein discloses a source electrode) of the first transistor (Fig. 1B; wherein figure shows a transistor), and the electrode pattern (16A; Fig. 1B and 2D) contacts the first electrode 16A; Fig. 1B; wherein discloses a source electrode) of the first transistor (Fig. 1B; wherein figure shows a transistor).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke’s display device by applying a method of manufacturing the transistor, as taught by Amari, so to use a display device with a method of manufacturing the transistor for providing a thin film transistor that is reduced in contact resistance and improved in EM resistance, a method of manufacturing the thin film transistor, and an electronic apparatus (Paragraph [0007]).
Claims 5 and 13, Ke (Fig. 1-23) discloses wherein the bridge pattern (L1/107; Fig. 8) is connected to an electrode of a transistor (M4; Fig. 9) other than the first transistor (M1; Fig. 9).
Claims 6 and 15, Amari (Fig. 1A-20B) discloses wherein the first semiconductor pattern (34; Fig. 6A; Paragraph [0091]) includes a first electrode (16A; Fig. 6B) of the first transistor (3; Fig. 6B),
the first electrode (16A; Fig. 6B) of the first transistor (3; Fig. 6B) includes first sub-electrodes (34A1-34A3; Fig. 6A) spaced apart from each other (Fig. 6A; wherein electrode 16a is connected to the semiconductor 34 through the three respective through holes 34A1-34A3),
the electrode pattern (16A; Fig. 6B) includes sub-electrode patterns (34A1-34A3; Fig. 6A) spaced apart from each other (Fig. 6A; wherein electrode 16a is connected to the semiconductor 34 through the three respective through holes 34A1-34A3),
the sub-electrode patterns (34A1-34A3; Fig. 6A) contact corresponding first sub-electrodes (16A; Fig. 6B), and
the bridge pattern (Fig. 2D; wherein figure shows electrode 16A connected to pattern below semiconductor) connects the sub-electrode patterns (16A; Fig. 6B and 6A).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke’s display device by applying a method of manufacturing the transistor, as taught by Amari, so to use a display device with a method of manufacturing the transistor for providing a thin film transistor that is reduced in contact resistance and improved in EM resistance, a method of manufacturing the thin film transistor, and an electronic apparatus (Paragraph [0007]).
Claim 7, Ke (Fig. 1-23) discloses wherein the bridge pattern (Out; Fig. 9) is a scan line (Paragraph [0140]; Fig. 22 and 23) that connects a pixel (P; Fig. 23) and a scan driver (010; Fig. 23).
Claim 8, Ke (Fig. 1-23) discloses wherein the bridge pattern (Out; Fig. 9) is an emission line (Paragraph [0140]; wherein discloses “The gate drive signal output by the shift register circuit 100 may be any one of the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, or the light emission control signal EM”; Fig. 23; EM; Fig. 24) that connects a pixel (P; Fig. 23) and an emission driver (010; Fig. 23).
Claim 14, Ke (Fig. 1-23) discloses wherein a second electrode (m33; Fig. 11; In and M31; Fig. 10) of the first transistor (Paragraph [0089]; wherein discloses transistor M3 may be an n-type transistor) receives a scan start signal (STV; Fig. 21) or a scan signal of a previous stage (Fig. 21; wherein figure shows stages other than the first stage receiving a scan signal of a previous stage at the input terminal IN).
Claim 16, Ke (Fig. 1-23) discloses wherein the first electrode (m14; Fig. 11) of the first transistor (M1; Fig. 10 and 11) is connected to a gate electrode of at least one of the plurality of first semiconductor transistors (M5; Fig. 10; wherein figure shows electrode of M1 is connected to node N2 which is connected to the transistor M5 which is a p-type transistor).
Claim 17, Ke (Fig. 1-23) discloses wherein the first electrode (m14; Fig. 11) of the first transistor (M1; Fig. 10) is further connected to a gate electrode of at least one of the plurality of second semiconductor transistors (M5; Fig. 10; Paragraph [0098]; wherein discloses transistor M5 can be an n-type transistor; Fig. 10; wherein figure shows electrode of transistor M1 connected to node N2 which is connected to the gate of transistor M5).
Claim 18, Ke (Fig. 1-23) discloses wherein the bridge pattern (Out; Fig. 10) is a scan line (Fig. 23).
Claim 19, Ke (Fig. 1-23) discloses wherein the first transistor (M1; Fig. 8) is connected to (m14 and m24; Fig. 8) at least one of the plurality of first semiconductor transistors (M2; Fig. 8).
Claim 20, Ke (Fig. 1-23) discloses wherein the first transistor (M1; Fig. 8) is connected to at least one of the plurality of first semiconductor (M2; Fig. 8) transistors through the electrode pattern (m14 and m24; Fig. 8).
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ke et al (US 2024/0395195 A1) in view of Amari (US 2015/0021572 A1) as applied to claims 1 and 9 above, and further in view of Oh (US 2016/0005804 A1).
Claims 3 and 11, Ke in view of Amari discloses the display device of claim 1 and the scan driver of claim 9.
Ke in view of Amari does not expressly disclose wherein the etched portion is a hydrogen exhaust port.
Oh (Fig. 10A and 10B) discloses wherein the etched portion (124S, 124D, and 164D; Fig. 10B) is a hydrogen exhaust port (Paragraph [0064-0065]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Ke in view of Amari’s display device by applying a method of injecting hydrogen, as taught by Oh, so to use a display device with a method of injecting hydrogen for providing improve interface characteristics and prevent charge movement from being trapped (Paragraph [0064]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam J Snyder/Primary Examiner, Art Unit 2623 02/11/2026