DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
The double patent rejection, as indicated in office action dated 5/28/2026, requires a TD to overcome; and the applicant indicated a TD may be filed in a later date when it is the only pending issue, as indicated in a filing dated 8/19/2026.
Allowable Subject Matter
Claim 109 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 103-107, 111-120, 123, 126-127 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noda et al. (PGPUB 20050285862), hereinafter as Noda.
Regarding claim 103, Noda teaches a storage device comprising:
an array comprising storage cells arranged as a plurality of rows of storage cells and a plurality of columns of storage cells (Fig 16, array 104), wherein individual ones of the storage cells comprise at least two transistors (Fig 17, 8 transistors per cell); and
a hardware controller (Fig 16, row decoder A/B) coupled to the array, the hardware controller capable of receiving an operation as input, and responsive to the operation, controlling row major access and column major access to the array (Fig 17, WLA in col direction and WLB in row direction).
Regarding claim 104, Noda teaches rows of the array are accessed in row major access and columns of the array are accessed in column major access, and row major access and column major access of the array are accesses of the array in different directions (Fig 17).
Regarding claim 105, Noda teaches the array further comprises a plurality of row bit lines and a plurality of column bit lines, wherein individual ones of the plurality of row bit lines are coupled to individual ones of row major storage cells, and wherein individual ones of the plurality of column bit lines are coupled to individual ones of column major storage cells (Fig. 17).
Regarding claim 106, Noda teaches the hardware controller is further coupled to data buffers comprising at least one first data buffer that is associated with row major access, and at least one second data buffer that is associated with column major access (Fig 17, SA group a/b).
Regarding claim 107, Noda teaches the at least one first data buffer is used to send and/or receive and/or hold at least a plurality of row values, and the at least one second data buffer is used to send and/or receive and/or hold at least a plurality of column values (Fig 17).
Regarding claim 111, Noda teaches a storage device comprising: an arrangement of storage cells (Fig 16), wherein individual ones of the storage cells comprise at least two transistors (Fig 17, 8 transistors per cell), the arrangement comprising a plurality of rows of storage cells and a plurality of columns of storage cells, the arrangement further comprising a plurality of row word lines and a plurality of column word lines (Fig 17), wherein individual ones of the plurality of row word lines are coupled to one or more members of individual ones of the plurality of rows of storage cells, and wherein individual ones of the plurality of column word lines are coupled to one or more members of individual ones of the plurality of column of storage cells (Fig 17).
Regarding claim 112, Noda teaches dram cells ([0203]).
Regarding claim 113, Noda teaches hardware capable of receiving commands or instructions and being responsive to the received commands or instructions to control and/or drive individual ones of the plurality of row word lines and/or individual ones of the plurality of column word lines to provide access to corresponding storage cells (Fig. 16).
Regarding claim 114, Noda teaches a row address decoder coupled to and driving individual ones of the plurality of row word lines and controlling individual ones of corresponding storage cells coupled to corresponding individual ones of the plurality of row word lines (Fig 16, row decoder A/B).
Regarding claim 115, Noda teaches a column address decoder coupled to and driving individual ones of the plurality of column word lines and controlling individual ones of corresponding storage cells coupled to the corresponding individual ones of the plurality of column word lines (Fig 16, row decoder A/B).
Regarding claim 116, Noda teaches arrangement of storage cells further comprises a plurality of row bit lines and a plurality of column bit lines, wherein an individual one of the plurality of row bit lines is coupled to a first set of one or more individual ones of a plurality of storage cells, and wherein an individual one of the plurality of column bit lines is coupled to a second set of one or more individual ones of a plurality of storage cells (Fig 16/17).
Regarding claim 117, Noda teaches a data buffer is coupled to the plurality of row bit lines (Fig 16, it is well known buffer is comprised in a SA/IO circuit).
Regarding claim 118, Noda teaches a data buffer is coupled to the plurality of column bit lines (Fig 16, it is well known buffer is comprised in a SA/IO circuit).
Regarding claim 119, Noda teaches to control operation of the data buffer to receive a row of data values stored in the storage device (Fig 16, it is well known buffer is comprised in a SA/IO circuit).
Regarding claim 120, Noda teaches to control access to the storage cells is configured to control operation of the data buffer to receive a column of data values stored in the storage device (Fig 16,).
Regarding claim 123, Noda teaches at least one storage cell is coupled to at least one individual one of the plurality of row bit lines and the at least one storage cell also coupled to at least one individual one of the plurality of column bit lines (Fig 16/17).
Regarding claim 126/127, Noda teaches the storage cells are static memory cells ([0202]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 108, 121-122, 124 is/are rejected under 35 U.S.C. 103 as being unpatentable over Noda.
Regarding claim 108/121/122, the examiner is taking note that it is well known in the field that a precharge circuit is used for precharging bit lines.
Regarding claim 124, the examiner is taking note that it is well known in the field that a storage device is implemented on a single semiconductor chip.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827
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