Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/23/2025 and 03/19/2026 have been considered by the examiner.
Oath/Declaration
Oath/Declaration as file 11/25/2024 is noted by the Examiner.
Claim Objections
Claim 3 is objected to because of the following informalities:
Claim 3 recites “The chip or wafer of claim 1, wherein a=90 um and d=45 um.” The claim dependency appears to be improper as there is no disclosure, nor explanation, of the terms “a” or “d” in Claim 1; the terms, and meaning of said terms in question, are introduced in Claim 2, therefore it appears that Claim 3 is actually dependent on Claim 2. Please make the proper corrections with regards to Claim dependency.
Note: For the purposes of this Office Action, Claim 3 will be treated as if it’s dependent on Claim 2; as Claim 3 appears to be meant to further limit Claim 2.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “…at least two electrical signals that can transfer from the at least two alignment marks to the at least two electrically conductive probe needles…” in lines 4-5 of Claim 1. It is not clear if the underlined limitation in question refers to the same “at least two electrically conducting alignment marks” disclosed earlier in Claim 1 or if it refers to a different “at least two alignment marks”. If this is the case, then please change the limitation in question to “the at least two electrically conducting alignment marks”.
Claim 7 recites the limitation “…wherein the electrically conducting alignment marks comprise segments of straight lines that are vertically shifted with respect to each other.” in lines 1-2 of Claim 7. It is not clear if the underlined limitation in question refers to the same “at least two electrically conducting alignment marks” disclosed earlier in Claim 1 or if it refers to a different “electrically conducting alignment marks”. If this is the case, then please change the limitation in question to “the at least two electrically conducting alignment marks”.
Claim 8 recites the limitation “…wherein the electrically conducting alignment marks comprise one or more metal crosses configured to be probed by an array of at least 3×3 probe needles.” in lines 1-2 of Claim 8. It is not clear if the underlined limitation in question refers to the same “at least two electrically conducting alignment marks” disclosed earlier in Claim 1 or if it refers to a different “electrically conducting alignment marks ”. If this is the case, then please change the limitation in question to “the at least two electrically conducting alignment marks”.
Claim 12 recites the limitation “…a processor and one or more executable software instructions programmed to correct alignment of the wafer chuck relative to the probe card based on the plurality of electrical signals.” in lines 6-8 of Claim 12. It is not clear if the underlined limitation in question refers to the same “electrical wafer chuck” disclosed earlier in Claim 1 or if it refers to a different “wafer chuck”. If this is the case, then please change the limitation in question to “the electrical wafer chuck”.
Claim 13 recites the limitation “…wherein the wafer chuck is rotatable separate from a lateral movement of the probe card.” in lines 1-2 of Claim 12. It is not clear if the underlined limitation in question refers to the same “electrical wafer chuck” disclosed earlier in Claim 1 or if it refers to a different “wafer chuck”. If this is the case, then please change the limitation in question to “the electrical wafer chuck”.
Claims 2-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 1.
Claims 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as they further limit Claim 12.
Please make the proper corrections.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 4-11 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Wu et al. US 2017/0184663 (Hereinafter Wu).
Regarding claim 1, Wu teaches a chip or wafer (Figs. 1A, 1B; wafer, 140; wafer testing system) comprising:
at least two electrically conducting alignment marks (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines) configured to contact at least two electrically conductive probe needles (Figs. 1A, 1B; probes, 130) on a probe card (Figs. 1A, 1B; probe card, 100);
at least two electrical signals (Figs. 1-2; [0002, 0016-0021]; electrical signals) that can transfer from the at least two alignment marks (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines) to the at least two electrically conductive probe needles (Figs. 1A, 1B; probes, 130); and
wherein the at least two electrical signals (Figs. 1-2; [0002, 0016-0021]; electrical signals) have a different voltage level or a different signal frequency than one another ([0114]; voltage levels).
Regarding claim 4, Wu further teaches the chip or wafer of claim 1, wherein the at least two electrically conducting alignment marks comprise at least two metal lines (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines) horizontally or vertically aligned to a line or array of probe needles (Figs. 1A, 1B; probes, 130).
Regarding claim 5, Wu further teaches the chip or wafer of claim 1, wherein the at least two electrically conducting alignment marks (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines) are diagonally arranged relative to a line or array of probe needles (Figs. 1A, 1B; probes, 130).
Regarding claim 6, Wu further teaches the chip of wafer of claim 1, wherein the at least two electrically conducting alignment marks (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines) form an angle between 5 to 85 degrees relative to a line or array of probe needles (Figs. 1A, 1B; probes, 130).
Regarding claim 7, Wu further teaches the chip or wafer of claim 1, wherein the electrically conducting alignment marks comprise segments of straight lines that are vertically shifted with respect to each other (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines).
Regarding claim 8, Wu further teaches the chip or wafer of claim 1, wherein the electrically conducting alignment marks comprise one or more metal crosses configured to be probed by an array of at least 3×3 probe needles (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines).
Regarding claim 9, Wu further teaches the chip or wafer of claim 1, wherein the at least two electrically conductive alignment marks are separated by at least 10 mm (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines).
Regarding claim 10, Wu further teaches the chip or wafer of claim 1, wherein the at least two electrical signals (Figs. 1-2; [0002, 0016-0021]; electrical signals) are used to calculate a rotational deviation of the chip or wafer (Figs. 1A, 1B; wafer, 140; wafer testing system) relative to the probe card (Figs. 1A, 1B; probe card, 100).
Regarding claim 11, Wu further teaches the chip or wafer of claim 1, wherein the at least two electrical signals (Figs. 1-2; [0002, 0016-0021]; electrical signals) are used to calculate a lateral deviation of the chip or wafer (Figs. 1A, 1B; wafer, 140; wafer testing system) relative to the probe card (Figs. 1A, 1B; probe card, 100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Dozier, II et al. US 2010/0244873 (Hereinafter Dozier).
Regarding claim 12, Wu teaches a system for probing a chip or wafer (Figs. 1A, 1B; wafer, 140; wafer testing system), comprising:
a probe card (Figs. 1A, 1B; probe card, 100) having a plurality of probe needles (Figs. 1A, 1B; probes, 130) for receiving a plurality of electrical signals (Figs. 1-2; [0002, 0016-0021]; electrical signals) from a plurality of electrically conducting alignment marks (Figs. 1-2; [0014, 0015, 0021, 0027]; two metal wires, metal lines) on the chip or wafer (Figs. 1A, 1B; wafer, 140; wafer testing system).
Wu does not specifically teach an electrical wafer chuck for mounting a chip or wafer for testing; and a processor and one or more executable software instructions programmed to correct alignment of the wafer chuck relative to the probe card based on the plurality of electrical signals.
However, Dozier does teach an electrical wafer chuck (Fig. 2; chuck, 204) for mounting a chip or wafer (Figs. 1, 7, 8; wafer, 802) for testing (Fig. 1; Wafer-level testing, 104); and a processor ([0054, 0081, 0090-0093]; processor, controller) and one or more executable software instructions programmed to correct alignment of the wafer chuck (Fig. 2; chuck, 204) relative to the probe card (Fig. 2; probe card, 208) based on the plurality of electrical signals ([0054, 0081, 0090-0093]; processor, controller).
It would have been obvious before the effective filing date of the claimed invention to modify the probe card and wafer testing system of Wu by implementing the teachings of Dozier regarding an electrical wafer chuck for mounting a chip or wafer for testing; and a processor and one or more executable software instructions programmed to correct alignment of the wafer chuck relative to the probe card based on the plurality of electrical signals; in order to allow “interchangeable interfaces to different testers to attach/detach quickly from the carrier, and allows connection devices to reduce requirement for a single intermediate connection device of a large area” (See Dozier; Abstract).
Regarding claim 13, the combination of Wu and Dozier teaches the system of claim 12, wherein Dozier further teaches wherein the wafer chuck (Fig. 2; chuck, 204) is rotatable separate from a lateral movement of the probe card (Fig. 2; probe card, 208).
Regarding claim 14, the combination of Wu and Dozier teaches the system of claim 13, wherein Dozier further teaches wherein the processor ([0054, 0081, 0090-0093]; processor, controller) and one or more executable software instructions are programmed to rotate the electrical wafer chuck and laterally move the probe card based on the plurality of electrical signals ([0054, 0081, 0090-0093]; processor, controller).
Allowable Subject Matter
The following is an examiner’s statement of reasons for allowance:
Regarding claim 2, the prior art does not teach or suggest, in combination with the rest of the limitations of claim 1,
“…wherein: the at least two electrically conductive probe needles are spaced by a distance of a, or by multiples of a; the at least two electrically conducting alignment marks are shifted in x- or y-direction on the chip or wafer by a distance of d; and wherein a is not equal to d.”
Claims 3 is also allowed as it further limits objected claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ni et al. US 2010/0164524 - A ZIF connector, a semiconductor testing device using the ZIF connectors, and a semiconductor testing system using the ZIF connectors are proposed. The ZIF connector comprises a body portion and a clamping portion. The body portion is a print circuit board provided with circuit patterns, and further comprises a plurality of signal holes disposed on an upper part of the body portion for electrically connecting a plurality of corresponding signal cables and a plurality of electrical terminals disposed on a lower part of the body portion and arranged on two lateral sides of the body portion for electrically connecting a plurality of corresponding electrical pads of a substrate.
Dutta et al. US 2023/0170266 - A system includes a wafer including at least an electronic component and a probe pad including a built-in back-end-of-line (BEOL) interconnect structure to test the electronic component. The electronic component is tested by the probe pad without building full BEOL interconnect circuits on the wafer. The probe pad is aligned with the wafer by using alignment marks. A prober alignment camera is employed to locate the alignment marks.
Jang US 2012/0235697 - Systems and methods of testing semiconductor devices, the system including a tester configured to evaluate electrical characteristics of a semiconductor device provided on a wafer, and a probe unit configured to transfer electrical signals used to test the semiconductor device between the tester and the semiconductor device. The probe unit may include: a housing; a wafer supporting member disposed in the housing to support the wafer; a printed circuit board disposed on the housing to transfer the electrical signals from and to the tester, and a probe card disposed opposite the wafer supporting member, in the housing. The probe card may include probe pins to deliver the electrical signal from and to the semiconductor device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAUL J RIOS RUSSO whose telephone number is (571)270-3459. The examiner can normally be reached Monday-Friday: 10am-6pm, EST.
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/RAUL J RIOS RUSSO/Examiner, Art Unit 2858
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