DETAILED ACTION
Claims 1-20 filed November 20th 2024 are pending in the current action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-11, and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US2023/0170805) in view of Okajima et al. (US2014/0059317)
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Figure 1 of Wei
Consider claim 1, where Wei teaches a voltage generator comprising: an input circuit configured to output a first request signal and a second request signal in response to first and second voltage data signals and first and second feedback voltages; (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages. Please refer to Applicant’s Fig 2 and ¶55.) a FIFO and priority logic configured to output one of first and second selection signals as an active level in synchronization with a valley current signal when at least one of the first and second request signals is at an active level; (See Wei Fig. 1, 8 and ¶33, 105-110 The signal loaded first into the FIFO and priority logic 123 will be also first dumped out at the positive edge of the valley current VC signal. Only one output is selected in each time slot between two VC signals. Please refer to Applicant’s Fig. 4 and ¶94-95) switching logic configured to output a plurality of switching signals in response to one of the first and second selection signals, which is the active level; (See Wei Figs. 1, 10 and ¶34, 112-115, 135 the TMCCT control logic 125 generates the high signals ST.sub.1 and ST.sub.3. In response to the high signals ST.sub.1 and ST.sub.3, the logic control and gate driver 150 generates the high switch control signals S.sub.1 and S.sub.3 to conduct the switches SW1 and SW3.) and a voltage converter configured to convert an input voltage into first and second output voltages, respectively, in response to the plurality of switching signals, and to output the first and second feedback voltages corresponding to the first and second output voltages, respectively, (See Wei Fig. 1 and ¶24-29 where The power stage 110 of the SIMO DC-DC converter 100 generates a plurality of output voltages V.sub.O1, V.sub.O2, ..., V.sub.Om (m being a positive integer) from an input voltage V.sub.IN. The switches SW1, SW2, SW3, SWO.sub.1, SWO.sub.2, ..., SWO.sub.m are controlled by a plurality of switch control signals S.sub.1, S.sub.2, S.sub.3, S.sub.O1, S.sub.O2, ..., S.sub.Om, respectively. The switch control signals S.sub.1, S.sub.2, S.sub.3, S.sub.O1, S.sub.O2, ..., S.sub.Om are generated by the control circuit 120 and the logic control and gate driver 150.) and wherein when the first and second request signals are simultaneously at the active level, the FIFO and priority logic outputs one of the first and second selection signals at the active level depending on a priority. (See Wei Fig. 8 and ¶107-110 where While more than one of the input signals concurrently go high at the positive edge of the valley current VC, all the high signals will be loaded into the FIFO and priority logic 123 with higher priority signals being placed first into the FIFO and priority logic 123.)
Wei teach synchronization to a valley current signal. (See Wei Fig. 8 where the CT outputs are synchronized to the VC signal) However, Wei does not explicitly teach clock. However, in an analogous field of endeavor Okajima teaches a clock. (See Okajima ¶48 where the FIFO memory 40 outputs the data RD0 in a cycle (e.g. cycle twice as long as that of a clock signal for display) corresponding to a request timing (e.g. clock signal for display) of the display unit 15 whilst the data readout is permitted.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the valley current of Wei such that it corresponds to a request timing of a display as taught by Okajima. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of adhering to the data readout permitted times of a larger system.
Consider claim 4, where Wei in view of Okajima teaches the voltage generator of claim 1, wherein the FIFO and priority logic outputs the first selection signal at the active level when the first and second request signals are simultaneously at the active level. (See Wei Fig. 1, 8 and ¶33, 105-110 The signal loaded first into the FIFO and priority logic 123 will be also first dumped out at the positive edge of the valley current VC signal. Only one output is selected in each time slot between two VC signals. Please refer to Applicant’s Fig. 4 and ¶94-95)
Consider claim 5, where Wei in view of Okajima teaches the voltage generator of claim 1, wherein, when a period of the clock signal is ‘P’ and the first and second request signals are simultaneously at the active levels, the FIFO and priority logic outputs the first and second selection signals such that a period of the first selection signal is 2P or less. (See Wei Fig. 8 and ¶110 where As shown in FIG. 8, at the second positive edge of the valley current VC, the input signals CP.sub.2 and CP.sub.3 go high at the same time. It is assumed that the priority is CP.sub.1>CP.sub.2>CP.sub.3... > CP.sub.N. The high signals CP.sub.2 and CP.sub.3 will be loaded into the FIFO and priority logic 123. In details, the high signal CP.sub.2 having priority higher than the high signal CP.sub.3 is first placed into the FIFO and priority logic 123, and the first-loaded high signal CP.sub.2 is first dumped out as the signal CT.sub.2 at the second positive edge of the valley current VC. Then, the high signal CP.sub.3 having lower priority is placed into the FIFO and priority logic 123, and the second-loaded high signal CP.sub.3 is second dumped out as the signal CT.sub.3 at the third positive edge of the valley current VC. Thus, dumping 2 loaded values after 2 positive edges of VC)
Consider claim 6, where Wei in view of Okajima teaches the voltage generator of claim 1, wherein the input circuit further outputs a third request signal in response to a third data signal and a third feedback voltage, wherein the FIFO and priority logic outputs any one of the first, second, and third selection signals in synchronization with the clock signal at the active level when at least one of the first, second, and third request signals is at the active level, wherein the switching logic outputs the plurality of switching signals in response to one of the first, second, and third selection signals, which is the active level, and wherein the voltage converter converts the input voltage into a third output voltage in response to the plurality of switching signals and further outputs a third feedback voltage corresponding to the third output voltage. (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages. Additionally, m=3 for the purposes of this claim. Please refer to Applicant’s Fig 2 and ¶55.)
Consider claim 7, where Wei in view of Okajima teaches the voltage generator of claim 6, wherein the first request signal has a higher priority than the second request signal, and the second request signal has a higher priority than the third request signal. (See Wei Fig. 8 and ¶110 where It is assumed that the priority is CP.sub.1>CP.sub.2>CP.sub.3... > CP.sub.N. The high signals CP.sub.2 and CP.sub.3 will be loaded into the FIFO and priority logic 123.)
Consider claim 8, where Wei in view of Okajima teaches the voltage generator of claim 7, wherein, when a period of the clock signal is ‘P’ and the first, second, and third request signals are simultaneously at the active levels, the FIFO and priority logic outputs the first, second, and third selection signals such that a period of the first selection signal is 2P or less, and a period of each of the second and third selection signals is 4P or less. (See Wei Fig. 8 and ¶110 where As shown in FIG. 8, at the second positive edge of the valley current VC, the input signals CP.sub.2 and CP.sub.3 go high at the same time. It is assumed that the priority is CP.sub.1>CP.sub.2>CP.sub.3... > CP.sub.N. The high signals CP.sub.2 and CP.sub.3 will be loaded into the FIFO and priority logic 123. In details, the high signal CP.sub.2 having priority higher than the high signal CP.sub.3 is first placed into the FIFO and priority logic 123, and the first-loaded high signal CP.sub.2 is first dumped out as the signal CT.sub.2 at the second positive edge of the valley current VC. Then, the high signal CP.sub.3 having lower priority is placed into the FIFO and priority logic 123, and the second-loaded high signal CP.sub.3 is second dumped out as the signal CT.sub.3 at the third positive edge of the valley current VC. Thus, dumping 3 loaded values after 3 positive edges of VC)
Consider claim 9, where Wei in view of Okajima teaches the voltage generator of claim 1, wherein the first and second voltage data signals are signals corresponding to target voltage levels of each of the first and second output voltages. (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages corresponding to the output voltages. Please refer to Applicant’s Fig 2 and ¶55.)
Consider claim 10, where Wei in view of Okajima teaches the voltage generator of claim 1, wherein the voltage converter includes a single inductor multiple output structure. (See Wei ¶137 ne embodiment of the application provides a single inductor multiple-output (or SIMBO) DC-DC converter)
Consider claim 11, where Wei teaches a voltage generator configured to provide first and second driving voltages to a gate driver, and wherein the voltage generator includes: an input circuit configured to output a first request signal and a second request signal in response to first and second voltage data signals and first and second feedback voltages; (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages. Please refer to Applicant’s Fig 2 and ¶55.) a FIFO and priority logic configured to output one of first and second selection signals as an active level in synchronization with a valley current signal when at least one of the first and second request signals is at an active level; (See Wei Fig. 1, 8 and ¶33, 105-110 The signal loaded first into the FIFO and priority logic 123 will be also first dumped out at the positive edge of the valley current VC signal. Only one output is selected in each time slot between two VC signals. Please refer to Applicant’s Fig. 4 and ¶94-95) switching logic configured to output a plurality of switching signals in response to one of the first and second selection signals, which is the active level; (See Wei Figs. 1, 10 and ¶34, 112-115, 135 the TMCCT control logic 125 generates the high signals ST.sub.1 and ST.sub.3. In response to the high signals ST.sub.1 and ST.sub.3, the logic control and gate driver 150 generates the high switch control signals S.sub.1 and S.sub.3 to conduct the switches SW1 and SW3.) and a voltage converter configured to convert an input voltage into first and second output voltages, respectively, in response to the plurality of switching signals, and to output the first and second feedback voltages corresponding to the first and second output voltages, respectively, (See Wei Fig. 1 and ¶24-29 where The power stage 110 of the SIMO DC-DC converter 100 generates a plurality of output voltages V.sub.O1, V.sub.O2, ..., V.sub.Om (m being a positive integer) from an input voltage V.sub.IN. The switches SW1, SW2, SW3, SWO.sub.1, SWO.sub.2, ..., SWO.sub.m are controlled by a plurality of switch control signals S.sub.1, S.sub.2, S.sub.3, S.sub.O1, S.sub.O2, ..., S.sub.Om, respectively. The switch control signals S.sub.1, S.sub.2, S.sub.3, S.sub.O1, S.sub.O2, ..., S.sub.Om are generated by the control circuit 120 and the logic control and gate driver 150.) and wherein when the first and second request signals are simultaneously at the active level, the FIFO and priority logic outputs one of the first and second selection signals at the active level depending on a priority. (See Wei Fig. 8 and ¶107-110 where While more than one of the input signals concurrently go high at the positive edge of the valley current VC, all the high signals will be loaded into the FIFO and priority logic 123 with higher priority signals being placed first into the FIFO and priority logic 123.)
Wei teach synchronization to a valley current signal. (See Wei Fig. 8 where the CT outputs are synchronized to the VC signal) However, Wei does not explicitly teach clock. However, in an analogous field of endeavor Okajima teaches a clock. (See Okajima ¶48 where the FIFO memory 40 outputs the data RD0 in a cycle (e.g. cycle twice as long as that of a clock signal for display) corresponding to a request timing (e.g. clock signal for display) of the display unit 15 whilst the data readout is permitted.) Therefore, it would have been obvious for one of ordinary skill in the art to modify the valley current of Wei such that it corresponds to a request timing of a display as taught by Okajima. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of adhering to the data readout permitted times of a larger system.
Wei teaches a gate driver, however Wei does not explicitly teach A display device comprising: a display panel; a scan driving circuit configured to provide a scan signal to the display panel; a data driving circuit configured to provide a data signal to the display panel; a driving controller configured to output first and second voltage data signals and a clock signal. However, in an analogous field of endeavor Okajima teaches a display device comprising: a display panel; a scan driving circuit configured to provide a scan signal to the display panel; a data driving circuit configured to provide a data signal to the display panel; a driving controller configured to output first and second voltage data signals and a clock signal. (See Okajima ¶36 where The output unit 33 sequentially outputs image data of each frame stored in the frame memory 13 to the display unit 15. As illustrated in FIG. 3A, image data FDA of one frame corresponding to the pixel number of the display unit 15 includes a plurality of (eight in FIG. 3A) line data L0 to L7. The image data FDA is, for example, YCbCr image data. Each line data L0 to L7 includes a plurality of (eight in FIG. 3A) pixel data D. In FIG. 3A, each pixel data D is illustrated as pixel data "DXY" with the position of the row of pixel data arranged in a horizontal direction denoted by X (X=0 to 7) and the position of the column of pixel data arranged in a vertical direction denoted by Y (Y=0 to 7). Thus, scan driving the horizontal direction and data driving the vertical direction). Therefore, it would have been obvious for one of ordinary skill in the art to modify Wei’s gate driver into a display device which commonly incorporates a gate/scan driver. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known components for known purposes.
Consider claim 14, where Wei in view of Okajima teaches the display device of claim 11, wherein the FIFO and priority logic outputs the first selection signal at the active level when the first and second request signals are simultaneously at the active level. (See Wei Fig. 1, 8 and ¶33, 105-110 The signal loaded first into the FIFO and priority logic 123 will be also first dumped out at the positive edge of the valley current VC signal. Only one output is selected in each time slot between two VC signals. Please refer to Applicant’s Fig. 4 and ¶94-95)
Consider claim 15, where Wei in view of Okajima teaches the display device of claim 11, wherein, when a period of the clock signal is ‘P’ and the first and second request signals are simultaneously at the active levels, the FIFO and priority logic outputs the first and second selection signals such that a period of the first selection signal is 2P or less. (See Wei Fig. 8 and ¶110 where As shown in FIG. 8, at the second positive edge of the valley current VC, the input signals CP.sub.2 and CP.sub.3 go high at the same time. It is assumed that the priority is CP.sub.1>CP.sub.2>CP.sub.3... > CP.sub.N. The high signals CP.sub.2 and CP.sub.3 will be loaded into the FIFO and priority logic 123. In details, the high signal CP.sub.2 having priority higher than the high signal CP.sub.3 is first placed into the FIFO and priority logic 123, and the first-loaded high signal CP.sub.2 is first dumped out as the signal CT.sub.2 at the second positive edge of the valley current VC. Then, the high signal CP.sub.3 having lower priority is placed into the FIFO and priority logic 123, and the second-loaded high signal CP.sub.3 is second dumped out as the signal CT.sub.3 at the third positive edge of the valley current VC. Thus, dumping 2 loaded values after 2 positive edges of VC)
Consider claim 16, where Wei in view of Okajima teaches the display device of claim 11, wherein the input circuit further outputs a third request signal in response to a third data signal and a third feedback voltage, wherein the FIFO and priority logic outputs any one of the first, second, and third selection signals at the active level in synchronization with the clock signal when at least one of the first, second, and third request signals is at the active level, wherein the switching logic outputs the plurality of switching signals in response to one of the first, second, and third selection signals, which is the active level, and wherein the voltage converter converts the input voltage into a third driving voltage in response to the plurality of switching signals and further outputs a third feedback voltage corresponding to the third driving voltage. (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages. Additionally, m=3 for the purposes of this claim. Please refer to Applicant’s Fig 2 and ¶55.)
Consider claim 17, where Wei in view of Okajima teaches the display device of claim 16, wherein the first request signal has a higher priority than the second request signal, and the second request signal has a higher priority than the third request signal. See Wei Fig. 8 and ¶110 where It is assumed that the priority is CP.sub.1>CP.sub.2>CP.sub.3... > CP.sub.N. The high signals CP.sub.2 and CP.sub.3 will be loaded into the FIFO and priority logic 123.)
Consider claim 18, where Wei in view of Okajima teaches the display device of claim 17, wherein, when a period of the clock signal is ‘P’ and the first, second, and third request signals are simultaneously at the active levels, the FIFO and priority logic outputs the first, second, and third selection signals such that a period of the first selection signal is 2P or less, and a period of each of the second and third selection signals is 4P or less. (See Wei Fig. 8 and ¶110 where As shown in FIG. 8, at the second positive edge of the valley current VC, the input signals CP.sub.2 and CP.sub.3 go high at the same time. It is assumed that the priority is CP.sub.1>CP.sub.2>CP.sub.3... > CP.sub.N. The high signals CP.sub.2 and CP.sub.3 will be loaded into the FIFO and priority logic 123. In details, the high signal CP.sub.2 having priority higher than the high signal CP.sub.3 is first placed into the FIFO and priority logic 123, and the first-loaded high signal CP.sub.2 is first dumped out as the signal CT.sub.2 at the second positive edge of the valley current VC. Then, the high signal CP.sub.3 having lower priority is placed into the FIFO and priority logic 123, and the second-loaded high signal CP.sub.3 is second dumped out as the signal CT.sub.3 at the third positive edge of the valley current VC. Thus, dumping 3 loaded values after 3 positive edges of VC)
Consider claim 19, where Wei in view of Okajima teaches the display device of claim 11, wherein the voltage converter includes a single inductor multiple output structure. (See Wei ¶137 ne embodiment of the application provides a single inductor multiple-output (or SIMBO) DC-DC converter)
Consider claim 20, where Wei in view of Okajima teaches the display device of claim 11, wherein the first and second voltage data signals are signals corresponding to target voltage levels of each of the first and second driving voltages. (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages corresponding to the output voltages. Please refer to Applicant’s Fig 2 and ¶55.)
Claim(s) 2, 3, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of Okajima as applied to claim 1 above, and further in view of Cahill (US5,583,536)
Consider claim 2, where Wei in view of Okajima teaches the voltage generator of claim 1, wherein the input circuit includes: a first amplifier configured to compare the first feedback voltage with the first reference voltage and to output the first request signal; and a second amplifier configured to compare the second feedback voltage with the second reference voltage and to output the second request signal. (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages. Please refer to Applicant’s Fig 2 and ¶55.) however Wei does not explicitly teach a first digital-to-analog converter configured to convert the first voltage data signal to a first reference voltage; a second digital-to-analog converter configured to convert the second voltage data signal to a second reference voltage However, in an analogous field of endeavor Cahill teaches a first digital-to-analog converter configured to convert the first voltage data signal to a first reference voltage. (See Cahill Fig. 5 and col 6 line 15-37 where The voltage comparator 522 detects the difference between the voltage on the transmission line 530 and the voltage derived from the reference DAC 516 video current across the reference resistor 524.) Thus, it would be obvious for one of ordinary skill in the art to modify the first and second amplifiers of Wei to take a signal from a reference DAC as taught by Cahill. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known methods of converting digital video signals into analog signals
Consider claim 3, where Wei in view of Okajima in view of Cahill teaches the voltage generator of claim 2, wherein the first amplifier outputs the first request signal at the active level when a voltage level of the first feedback voltage is lower than or equal to the first reference voltage. (See Wei ¶32 where he plurality of voltage comparators 121_1~121_m generate the plurality of voltage comparator output signals CP.sub.1~CP.sub.m as high when the output voltages V.sub.O1, V.sub.O2, ... Vom are lower than the plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively.)
Consider claim 12, where Wei in view of Okajima teaches the display device of claim 11, wherein the input circuit includes: a first amplifier configured to compare the first feedback voltage with the first reference voltage and to output the first request signal; and a second amplifier configured to compare the second feedback voltage with the second reference voltage and to output the second request signal. (See Wei Fig. 1 (replicated above) and ¶32 where the plurality of voltage comparators 121_1~121_m generate a plurality of voltage comparator output signals CP.sub.1~CP.sub.m based on the output voltages V.sub.O1, V.sub.O2, ... Vom and a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively. Thus, voltage comparator output signals CP.sub.1~CP.sub.m serve as request voltages, a plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, serve as voltage data signals, and output voltages V.sub.O1, V.sub.O2, ... Vom serve as feedback voltages. Please refer to Applicant’s Fig 2 and ¶55.) however Wei does not explicitly teach a first digital-to-analog converter configured to convert the first voltage data signal to a first reference voltage; a second digital-to-analog converter configured to convert the second voltage data signal to a second reference voltage However, in an analogous field of endeavor Cahill teaches a first digital-to-analog converter configured to convert the first voltage data signal to a first reference voltage. (See Cahill Fig. 5 and col 6 line 15-37 where The voltage comparator 522 detects the difference between the voltage on the transmission line 530 and the voltage derived from the reference DAC 516 video current across the reference resistor 524.) Thus, it would be obvious for one of ordinary skill in the art to modify the first and second amplifiers of Wei to take a signal from a reference DAC as taught by Cahill. One of ordinary skill in the art would have been motivated to perform the modification for the advantage of/ benefit of using known methods of converting digital video signals into analog signals
Consider claim 13, where Wei in view of Okajima in view of Cahill teaches the display device of claim 12, wherein the first amplifier outputs the first request signal at the active level when a voltage level of the first feedback voltage is lower than or equal to the first reference voltage. (See Wei ¶32 where he plurality of voltage comparators 121_1~121_m generate the plurality of voltage comparator output signals CP.sub.1~CP.sub.m as high when the output voltages V.sub.O1, V.sub.O2, ... Vom are lower than the plurality of reference voltages VR.sub.1, VR.sub.2, ..., VR.sub.m, respectively.)
Conclusion
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WILLIAM LU
Primary Examiner
Art Unit 2624
/WILLIAM LU/Primary Examiner, Art Unit 2624
Prosecution Insights