DETAILED ACTION
This action is responsive to the following communications: the Application filed November 20, 2024, and the information disclosure statement (IDS) filed November 26, 2024 and March 25, 2025. This application is a CON of 18/235,935.
Claims 1-17 are pending. Claims 1-16 have been cancelled. Claim 17 is independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 26, 2024 and March 25, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tachimori (US 2003/0052661).
Regarding independent claim 17, the 4-transistor-based half power supply voltage generator circuit is one of the industrial standard architecture that has been widely reviewed and transformed into semiconductor IC. For support, see for example, Tachimori discloses a circuit (see FIG. 24) for generating a half Vdd voltage from a main on-chip supply voltage Vdd/Vss consisting of series connected transistors M1 and M2 in parallel with series connected transistors M3 and M4, connected between Vdd and Vss, with the half Vdd voltage output from a node connecting transistors M1, M2, M3 and M4, wherein transistors M1 and M3 function as a self-biased inverter and transistors M2 and M4 function as current sensing transistors (FIG. 24 and accompanying disclosure).
Apparatus claim 17 is rejected under 35 U.S.C 102(a)(1) as being clearly anticipated by Tachimori, figure 24, which is identical to instance applicant’s apparatus figure 9a.
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Because Tachimori’s apparatus is substantially identical to applicant’s claimed device, the claimed functions are presumed inherent. MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device does not possess the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); MPEP 2112.01(I) (quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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