DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Jo et al. (US 2021/0359079).
Regarding claim 1, Jo discloses an array substrate (Figs. 1-4) comprising: a gate line (151 & 152; Paragraph [0108]); a source line crossing the gate line (171a & 171b & 171c; Paragraph [0086]); a switching component disposed on a crossing portion of the gate line and the source line (T1 & T2 & T3; Paragraph [0069-0072]); a semiconductor film included in the switching component (Paragraph [0093]); a first insulating film disposed between a layer including the gate line and a layer including the semiconductor film (120; Paragraph [0100]); and a second insulating film disposed between a layer including the semiconductor film and a layer including the source line (111; Paragraph [0092]), wherein the source line overlaps the gate line via the first insulating film and the second insulating film (Fig. 4, 152 8 120 & 171B & 171C).
Regarding claim 2, Jo further discloses wherein the switching component includes a source electrode that is connected to the semiconductor film, the source line is connected to the source electrode and is connected to the semiconductor film via the source electrode, and the source electrode is disposed between the first insulating film and the second insulating film (Fig. 4, 111 & 120 & 2131; Paragraph [0096]).
Regarding claim 3, Jo further discloses wherein the source electrode does not overlap the gate line (Fig. 4, 2131 & 151 & 152).
Regarding claim 4, Jo discloses further comprising a relay electrode (179; Paragraph [0124]), wherein the switching component includes a drain electrode that is connected to the semiconductor film (2133; Paragraph [0093]), the relay electrode is connected to the drain electrode and is connected to the semiconductor film via the drain electrode (Paragraph [0126]), and the drain electrode is disposed between the first insulating film and the second insulating film (Fig. 4, 2133 & 111 & 120).
Regarding claim 5, Jo further discloses the array substrate according to claim 1; and an opposed substrate opposed to the array substrate (210; Paragraph [0221]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANNE M HINES whose telephone number is (571)272-2285. The examiner can normally be reached on M-F: 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Greece, can be reached on 571-272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Anne M Hines/
Primary Examiner
Art Unit 2879
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