DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 11/20/2024. Claims 1-20 have been cancelled. Claims 21-40 are pending in the Application, of which Claims 21, 38 and 40 are independent.
Continuity/Priority Information
The present Application 18954320 filed 11/20/2024 is a Continuation of 18318464, filed 05/16/2023, now U.S. Patent No. 12,345,762 and is a Continuation of 16940809, filed 07/28/2020, now U.S. Patent No. 11,686,766 and claims foreign priority to REPUBLIC OF KOREA, Application 10-2019-0175903, filed 12/27/2019.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/20/2024, 12/03/2024 and 03/19/2025 is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the IDS has been considered by the examiner.
Claim Objections
Claim 31-37 are objected to because of the following informalities:
Claim 31, “wherein the temperature-variant voltage is varied” change to “wherein the temperature-variant voltage varies” to recite an active voice. Any Claims not specifically mentioned above are also objected, due to their dependency on an objected claim. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-40 are rejected under 35 U.S.C. 103 as being unpatentable over MA et al. (Pub. No. US 20210088389) in view of KUMAHARA et al. (Pub. No. US 20180156675) Pub. Date: 2018-06-07.
Regarding independent Claims 21, 38 and 40, MA discloses systems and methods for calibrating temperature sensors, comprising:
an analog circuit configured to generate a measurement reference voltage that is fixed regardless of an operation temperature and a temperature-variant voltage that varies depending on the operation temperature; [0039] FIG. 2 depicts an example implementation of the current source 102 shown in FIG. 1. As shown in FIG. 2, the reference voltage generator 110 may include a bandgap voltage reference circuit 250, and the voltage-to-current controller 112 may include a voltage-controlled current source 254. The bandgap voltage reference circuit 250 may generate a reference voltage (e.g., V.sub.REF 114) that is temperature independent and may provide the reference voltage (e.g., V.sub.REF 114) to the voltage-controlled current source 254.
an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage in a normal mode and generate a second digital code based on a test signal in a test mode; [0041] an analog-to-digital converter (ADC) 358 that is configured to encode the amplified voltage outputs from the temperature sensor 350. As shown in FIG. 3, the amplified PTAT voltage (V.sub.PTAT) 356 (e.g., αΔV.sub.BE) may be provided to the ADC 358, which may convert the amplified PTAT voltage (V.sub.PTAT) 356 to digital temperature data 126.
an analog built-in self-test (BIST) circuit configured to monitor whether at least one monitoring voltage of the analog circuit is within a respective predetermined range; [0047] Referring back to FIG. 1, in one embodiment, the voltage window generator circuit 106 “analog built-in self-test (BIST)” may control (e.g., increase or decrease) the width of the voltage window (e.g., also referred to as the gain of the voltage window generator circuit 106) in response to a first digital control input 128. For example, and as explained in greater detail with reference to FIG. 5, the first digital control input 128 may be an N-bit digital value and the voltage window generator circuit 106 may generate the high reference voltage (V.sub.REF_H) 120 and the low reference voltage (V.sub.REF_L) 122 based on the N-bit digital value.
a digital BIST circuit configured to apply the test signal to the analog-digital converter circuit in the test mode, and generate an alarm signal indicating an operation state of the analog-digital converter circuit.
[0047] the processing circuit 101 “digital BIST circuit” may set and/or adjust the first digital control input 128 based on the digital temperature data 126 received from the temperature sensor circuit 124. In some embodiments, the first digital control input 128 (e.g., the N-bit digital value) may be a default value based on prior testing and/or calibration procedures performed on the temperature sensor 350. For example, the processing circuit 101 may be a central processing unit (CPU) of a wireless communication device (e.g., a smartphone, tablet, personal computer, etc.). The operation of the voltage window generator circuit 106 will now be described with reference to FIG. 5.
Regarding independent Claims 21, 38 and 40, and dependent Claims 22-25, 27, 28, 39, MA does not explicitly disclose “a digital BIST circuit configured to generate an alarm signal indicating an operation state of the analog-digital converter circuit”.
However, in analogous art, KUMAHARA discloses in Par. [0044] FIG. 3, a BIST circuit implemented in a digital circuit. [0045] The expectation comparison circuit 93 outputs the comparison result to at least one of a CPU 94 within a chip and the external terminal 95. The expectation comparison circuit 93 outputs, for example, the BIST result ‘Pass’ to at least one of the CPU 94 and the external terminal 95 when the input signal and the expect value are matched. When the input signal and the expect value are not matched, the expectation comparison circuit 93 outputs the BIST result ‘Fail’ “alarm signal” to at least one of the CPU 94 and the external terminal 95.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement the BIST as taught by KUMAHARA in the calibration circuit of MA for the purpose of testing temperature sensor parameters in the test mode, as to confirm whether the temperature sensor in which the BIST circuit is disposed is normally operating or not.
Regarding Claim 26, MA discloses wherein the analog-digital converter circuit comprises: a scan voltage generator circuit configured to generate a plurality of scan voltages having different voltage levels; [0046] FIG. 3, the ADC 358 may convert the amplified PTAT voltage (V.sub.PTAT) values 356 to digital temperature data 126 based on high and low reference voltage values provided to the ADC 358. Therefore, in one example, if the temperature sensor 350 includes the first temperature sensor associated with the PTAT slope 402 with the range 406 (e.g., 0.4V to 1.1V) of amplified PTAT voltage (V.sub.PTAT) values as described with reference to FIG. 4.
Regarding Claims 29, 30, 36, MA discloses a main sensing unit disposed at a main position and configured to generate a main sensing voltage; [0041] as shown in FIG. 3, the temperature sensor circuit 124 may include a temperature sensor 350 “sensing unit”. In some examples, the voltage output 352 from the temperature sensor 350 may be proportional to absolute temperature (PTAT). Accordingly, in these examples, the voltage output 352 may be referred to as a PTAT voltage (V.sub.PTAT).
Regarding Claims 31-34, 37, MA discloses a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature; [0039] As shown in FIG. 2, the reference voltage generator 110 may include a bandgap voltage reference circuit 250, and the voltage-to-current controller 112 may include a voltage-controlled current source 254. The bandgap voltage reference circuit 250 may generate a reference voltage (e.g., V.sub.REF 114) that is temperature independent and may provide the reference voltage (e.g., V.sub.REF 114) to the voltage-controlled current source 254.
Regarding Claim 35, MA discloses wherein the analog BIST circuit comprises: a measurement reference voltage divider circuit configured to generate a first measurement reference division voltage; [0047] Referring back to FIG. 1, in one embodiment, the voltage window generator circuit 106 “analog built-in self-test (BIST)” may control (e.g., increase or decrease) the width of the voltage window (e.g., also referred to as the gain of the voltage window generator circuit 106) in response to a first digital control input 128.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,686,766. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant include every limitation of the Claims recited in the U.S. Patent No. 11,686,76 , and thus anticipate the Claims of the instant Application. (See, TABLE A: Claims comparison). Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
TABLE A: Double Patenting Claims comparison
18954320 Instant Application Claims
(U.S. Patent No. 11,686,766) Claims
Independent Claim 21. A temperature measurement circuit comprising:
an analog circuit configured to generate a measurement reference voltage that is fixed regardless of an operation temperature and a temperature-variant voltage that varies depending on the operation temperature;
an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage in a normal mode and generate a second digital code based on a test signal in a test mode;
an analog built-in self-test (BIST) circuit configured to monitor whether at least one monitoring voltage of the analog circuit is within a respective predetermined range; and
a digital BIST circuit configured to apply the test signal to the analog-digital converter circuit in the test mode, and based on the second digital code, generate an alarm signal indicating an operation state of the analog-digital converter circuit.
Independent Claim 1. A temperature measurement circuit comprising:
a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature;
a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage;
a sensing circuit configured to generate a temperature-variant voltage based on a bias current, wherein the temperature-variant voltage is varied depending on the operation temperature; an
analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage; and
an analog built-in self-test (BIST) circuit configured to generate a first flag signal indicating whether the band-gap reference voltage is within a first predetermined range, a second flag signal indicating whether the measurement reference voltage is within a second predetermined range, and a third flag signal indicating whether a bias voltage corresponding to the bias current is within a third predetermined range.
Claim 7. a digital BIST circuit configured to apply a test signal instead of the temperature-variant voltage to the analog-digital converter circuit, receive a second digital code from the analog-digital converter circuit, and generate a plurality of alarm signals based on the second digital code, wherein the plurality of alarm signals indicate an operation state of the analog-digital converter circuit.
Independent Claim 38. A temperature measurement circuit comprising:
an analog-digital converter circuit configured to generate a first digital code indicating an operation temperature based on a temperature-variant voltage in a normal mode and generate a second digital code based on a test signal in a test mode; and
a digital BIST circuit configured to apply the test signal to the analog-digital converter circuit in the test mode, and based on the second digital code, generate an alarm signal indicating an operation state of the analog-digital converter circuit.
Independent Claim 20. A built-in self-test (BIST) circuit configured to monitor a temperature detection circuit including an analog circuit and an analog-digital converter circuit, the BIST circuit comprising:
an analog BIST circuit configured to generate, for each of a plurality of monitoring voltages of the analog circuit, a respective flag signal indicating whether the monitoring voltage is within a respective predetermined range; and
a digital BIST circuit configured to apply a test signal to the analog-digital converter circuit in a test mode, and based on a response of the analog-digital converter circuit to the test signal, an alarm signal indicating an operation state of the analog-digital converter circuit.
Independent Claim 40. A temperature measurement circuit comprising:
a temperature detection circuit configured to generate a temperature-variant voltage that varies depending on an operation temperature, generate a first digital code indicating the operation temperature based on the temperature-variant voltage in a normal mode, and generate a second digital code based on a test signal in a test mode;
an analog built-in self-test (BIST) circuit configured to monitor whether at least one monitoring voltage of the temperature detection circuit is within a respective predetermined range; and
a digital BIST circuit configured to apply the test signal to the temperature detection circuit in the test mode, and based on the second digital code, generate an alarm signal indicating an operation state of the temperature detection circuit.
Independent Claim 19. A temperature measurement circuit comprising:
a temperature detection circuit comprising:
an analog circuit configured to generate a measurement reference voltage that is fixed regardless of an operation temperature and a temperature-variant voltage that varies depending on the operation temperature; and
an analog-digital converter circuit configured to generate a digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage; and
an analog built-in self-test (BIST) circuit configured to generate, for each of a plurality of voltages of the analog circuit, a respective flag signal indicating whether the voltage is within a respective predetermined range.
Claim 7. a digital BIST circuit configured to apply a test signal instead of the temperature-variant voltage to the analog-digital converter circuit, receive a second digital code from the analog-digital converter circuit, and generate a plurality of alarm signals based on the second digital code, wherein the plurality of alarm signals indicate an operation state of the analog-digital converter circuit.
22. wherein the digital BIST circuit comprises: a test signal generator circuit configured to generate a ramp voltage having a voltage level sequentially increasing or sequentially decreasing and to apply the ramp voltage as the test signal to the analog-digital converter circuit, wherein the digital BIST circuit is configured to generate at least one of a monotony alarm signal or a linearity alarm signal based on a plurality of values of the second digital code, wherein the monotony alarm signal indicates whether the second digital code increases or decreases monotonously, and wherein the linearity alarm signal indicates whether the second digital code varies uniformly.
8. wherein the digital BIST circuit comprises: a test signal generator circuit configured to generate a ramp voltage having a voltage level sequentially increasing or sequentially decreasing and to apply the ramp voltage as the test signal to the analog-digital converter circuit.
9. wherein the digital BIST circuit is configured to generate at least one of a monotony alarm signal or a linearity alarm signal based on a plurality of values of the second digital code, wherein the monotony alarm signal indicates whether the second digital code increases or decreases monotonously, and wherein the linearity alarm signal indicates whether the second digital code varies uniformly.
23. wherein the test signal has a voltage level corresponding to a center value of the second digital code, and wherein the digital BIST circuit is configured to apply the test signal to the analog-digital converter circuit to generate an offset alarm signal indicating whether a difference between a measured value of the second digital code and the center value of the second digital code is greater than a reference value.
10. wherein the test signal has a voltage level corresponding to a center value of the second digital code, and wherein the digital BIST circuit is configured to apply the test signal to the analog-digital converter circuit to generate an offset alarm signal indicating whether a difference between a measured value of the second digital code and the center value of the second digital code is greater than a reference value.
24, 39. wherein the test signal has a higher voltage level than a voltage level corresponding to a maximum value of the second digital code, and wherein the digital BIST circuit is configured to apply the test signal to the analog-digital converter circuit to generate a stuck alarm signal indicating whether a first measured value of the second digital code is equal to the maximum value of the second digital code.
13. wherein the digital BIST circuit is configured to apply a first test signal having a higher voltage level than a voltage level corresponding to a maximum value of the second digital code to the analog-digital converter circuit when the pull-down switch is turned on, apply a second the test signal having a lower voltage level than a voltage level corresponding to a minimum value of the second digital code to the analog-digital converter circuit when the pull-up switch is turned on, and generate a floating alarm signal indicating at least one of whether a first measured value of the second digital code is equal to the maximum value of the second digital code or whether a second measured value of the second digital code is equal to the minimum value of the second digital code.
25. wherein the digital BIST circuit comprises: a pull-up resistor connected to a power supply voltage; a pull-up switch configured to control an electric connection between the pull-up resistor and an output node of the second digital code; a pull-down resistor connected to a ground voltage; and a pull-down switch configured to control an electric connection between the pull-down resistor and the output node of the second digital code, and wherein the digital BIST circuit is configured to apply a first test signal having a higher voltage level than a voltage level corresponding to a maximum value of the second digital code to the analog-digital converter circuit when the pull-down switch is turned on, apply a second test signal having a lower voltage level than a voltage level corresponding to a minimum value of the second digital code to the analog-digital converter circuit when the pull-up switch is turned on, and generate a floating alarm signal indicating at least one of whether a first measured value of the second digital code is equal to the maximum value of the second digital code or whether a second measured value of the second digital code is equal to the minimum value of the second digital code.
12. wherein the digital BIST circuit comprises: a pull-up resistor connected to a power supply voltage; a pull-up switch configured to control an electric connection between the pull-up resistor and an output node of the second digital code; a pull-down resistor connected to a ground voltage; and a pull-down switch configured to control an electric connection between the pull-down resistor and the output node of the second digital code.
13. wherein the digital BIST circuit is configured to apply a first test signal having a higher voltage level than a voltage level corresponding to a maximum value of the second digital code to the analog-digital converter circuit when the pull-down switch is turned on, apply a second the test signal having a lower voltage level than a voltage level corresponding to a minimum value of the second digital code to the analog-digital converter circuit when the pull-up switch is turned on, and generate a floating alarm signal indicating at least one of whether a first measured value of the second digital code is equal to the maximum value of the second digital code or whether a second measured value of the second digital code is equal to the minimum value of the second digital code.
26. wherein the analog-digital converter circuit comprises: a scan voltage generator circuit configured to generate a plurality of scan voltages having different voltage levels based on the measurement reference voltage and output the plurality of scan voltages one by one according to a unit scan time; a comparator circuit configured to generate a plurality of comparison result values by comparing the temperature-variant voltage with the plurality of scan voltages; a converter circuit configured to generate the second digital code based on the plurality of comparison result values; and a controller circuit configured to control the scan voltage generator circuit, the comparator circuit, and the converter circuit.
27. The temperature measurement circuit of claim 26, wherein the digital BIST circuit is configured to change the unit scan time between a first unit scan time and a second unit scan time longer than the first scan unit time, and generate a fluctuation alarm signal indicating whether a first measured value of the second digital code corresponding to the first unit scan time is equal to a second measured value of the second digital code corresponding to the second unit scan time.
28. wherein the digital BIST circuit comprises a counter configured to monitor operation timings of the analog-digital converter circuit, and wherein the digital BIST circuit is configured to generate at least one of a settling alarm signal or a conversion alarm signal using the counter, wherein the settling alarm signal indicates whether a total scan time for outputting the plurality of scan voltages from the scan voltage generator circuit is shorter than a first reference time, and wherein the conversion alarm signal indicates whether a conversion time for generating the second digital code by the converter circuit is shorter than a second reference time.
14. The temperature measurement circuit of claim 7, wherein the analog-digital converter circuit comprises: a scan voltage generator circuit configured to generate a plurality of scan voltages having different voltage levels based on the measurement reference voltage and output the plurality of scan voltages one by one according to a unit scan time; a comparator circuit configured to generate a plurality of comparison result values by comparing the temperature-variant voltage with the plurality of scan voltages; a converter circuit configured to generate the second digital code based on the plurality of comparison result values; and a controller circuit configured to control the scan voltage generator circuit, the comparator circuit, and the converter circuit.
15. The temperature measurement circuit of claim 14, wherein the digital BIST circuit is configured to change the unit scan time between a first unit scan time and a second unit scan time longer than the first scan unit time, and generate a fluctuation alarm signal indicating whether a first measured value of the second digital code corresponding to the first unit scan time is equal to a second measured value of the second digital code corresponding to the second unit scan time.
16. The temperature measurement circuit of claim 14, wherein the digital BIST circuit comprises a counter configured to monitor operation timings of the analog-digital converter circuit, and wherein the digital BIST circuit is configured to generate at least one of a settling alarm signal or a conversion alarm signal using the counter, wherein the settling alarm signal indicates whether a total scan time for outputting the plurality of scan voltages from the scan voltage generator circuit is shorter than a first reference time, and wherein the conversion alarm signal indicates whether a conversion time for generating the second digital code by the converter circuit is shorter than a second reference time.
29. a main sensing unit disposed at a main position and configured to generate a main sensing voltage that varies depending on a main operation temperature at the main position; and a plurality of local sensing units disposed at a plurality of local positions and configured to generate a plurality of local sensing voltages that vary depending on local operation temperatures at the plurality of local positions.
30. wherein the digital BIST circuit is configured to receive a first measured value of the second digital code corresponding to the main sensing voltage and a second measured value of the second digital code corresponding to a local sensing voltage provided from a local sensing unit nearest to the main sensing unit among the plurality of local sensing units, and generate a probe-check alarm signal indicating whether a difference between the first measured value and the second measured value is smaller than a reference value.
17. a main sensing unit disposed at a main position and configured to generate a main sensing voltage that varies depending on a main operation temperature at the main position; and a plurality of local sensing units disposed at a plurality of local positions and configured to generate a plurality of local sensing voltages that vary depending on local operation temperatures at the plurality of local positions.
18. wherein the digital BIST circuit is configured to receive a first measured value of the second digital code corresponding to the main sensing voltage and a second measured value of the second digital code corresponding to a local sensing voltage provided from a local sensing unit nearest to the main sensing unit among the plurality of local sensing units, and generate a probe-check alarm signal indicating whether a difference between the first measured value and the second measured value is smaller than a reference value.
31. wherein the analog BIST circuit comprises: a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature; a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage; and a sensing circuit configured to generate a temperature-variant voltage based on a bias current, wherein the temperature-variant voltage is varied depending on the operation temperature.
32. wherein the analog BIST circuit is configured to generate a first flag signal indicating whether the band-gap reference voltage is within a first predetermined range, a second flag signal indicating whether the measurement reference voltage is within a second predetermined range, and a third flag signal indicating whether a bias voltage corresponding to the bias current is within a third predetermined range.
33. wherein the analog BIST circuit comprises: a power supply voltage divider circuit configured to generate a power division voltage corresponding to a lowest limit level of the band-gap reference voltage by dividing a power supply voltage; and a comparator circuit configured to compare the band-gap reference voltage to the power division voltage, and activate the first flag signal in response to the band-gap reference voltage being lower than the lowest limit level of the band-gap reference voltage.
34. The temperature measurement circuit of claim 32, wherein the analog BIST circuit comprises: a band-gap reference voltage divider circuit configured to generate a first band-gap division voltage corresponding a highest limit level of the measurement reference voltage and a second band-gap division voltage corresponding to a lowest limit level of the measurement reference voltage by dividing the band-gap reference voltage; a measurement reference voltage divider circuit configured to generate a measurement division voltage by dividing the measurement reference voltage; and a comparator circuit configured to compare the measurement division voltage to the first band-gap division voltage and the second band-gap division voltage, and activate the second flag signal in response to the measurement reference voltage being higher than the highest limit level of the measurement reference voltage or lower than the lowest limit level of the measurement reference voltage.
2. wherein the analog BIST circuit comprises: a power supply voltage divider circuit configured to generate a power division voltage corresponding to a lowest limit level of the band-gap reference voltage by dividing a power supply voltage; and a comparator circuit configured to compare the band-gap reference voltage to the power division voltage, and activate the first flag signal in response to the band-gap reference voltage being lower than the lowest limit level of the band-gap reference voltage.
3. wherein the analog BIST circuit comprises: a band-gap reference voltage divider circuit configured to generate a first band-gap division voltage corresponding a highest limit level of the measurement reference voltage and a second band-gap division voltage corresponding to a lowest limit level of the measurement reference voltage by dividing the band-gap reference voltage; a measurement reference voltage divider circuit configured to generate a measurement division voltage by dividing the measurement reference voltage; and a comparator circuit configured to compare the measurement division voltage to the first band-gap division voltage and the second band-gap division voltage, and activate the second flag signal in response to is the measurement reference voltage being higher than the highest limit level of the measurement reference voltage or lower than the lowest limit level of the measurement reference voltage.
6. wherein the analog BIST circuit comprises: a band-gap reference voltage monitor circuit configured to activate the first flag signal based on the band-gap reference voltage and a power supply voltage in response to the band-gap reference voltage deviating from the first predetermined range; a measurement reference voltage monitor circuit configured activate the second flag signal based on the measurement reference voltage and the band-gap reference voltage in response to the measurement reference voltage deviating from the second predetermined range; and a bias voltage monitor circuit configured to activate the third flag signal based on the bias voltage and the measurement reference voltage in response to the bias voltage deviating from the third predetermined range.
35. wherein the analog BIST circuit comprises: a measurement reference voltage divider circuit configured to generate a first measurement reference division voltage corresponding to a highest limit level of the bias voltage and a second measurement reference division voltage corresponding to a lowest limit level of the bias voltage by dividing the measurement reference voltage; a current-voltage converter circuit configured to generate the bias voltage based on the bias current; and a comparator circuit configured to compare the bias voltage with the first measurement reference division voltage and the second measurement reference division voltage, and activate the third flag signal in response to the bias voltage being higher than the highest limit level of the bias voltage or lower than the lowest limit level of the bias voltage.
36. wherein the sensing circuit comprises a first current source configured to generate the bias current and the current-voltage converter circuit comprises a second current source configured to generate the bias current such that the first current source and the second current source form a current mirror.
4. wherein the analog BIST circuit comprises: a measurement reference voltage divider circuit configured to generate a first measurement reference division voltage corresponding to a highest limit level of the bias voltage and a second measurement reference division voltage corresponding to a lowest limit level of the bias voltage by dividing the measurement reference voltage; a current-voltage converter circuit configured to generate the bias voltage based on the bias current; and a comparator circuit configured to compare the bias voltage with the first measurement reference division voltage and the second measurement reference division voltage, and activate the third flag signal in response to the bias voltage being higher than the highest limit level of the bias voltage or lower than the lowest limit level of the bias voltage.
5. wherein the sensing circuit comprises a first current source configured to generate the bias current and the current-voltage converter circuit comprises a second current source configured to generate the bias current such that the first current source and the second current source form a current mirror.
37. wherein the analog BIST circuit comprises: a band-gap reference voltage monitor circuit configured to activate the first flag signal based on the band-gap reference voltage and a power supply voltage in response to the band-gap reference voltage deviating from the first predetermined range; a measurement reference voltage monitor circuit configured activate the second flag signal based on the measurement reference voltage and the band-gap reference voltage in response to the measurement reference voltage deviating from the second predetermined range; and a bias voltage monitor circuit configured to activate the third flag signal based on the bias voltage and the measurement reference voltage in response to the bias voltage deviating from the third predetermined range.
6. wherein the analog BIST circuit comprises: a band-gap reference voltage monitor circuit configured to activate the first flag signal based on the band-gap reference voltage and a power supply voltage in response to the band-gap reference voltage deviating from the first predetermined range; a measurement reference voltage monitor circuit configured activate the second flag signal based on the measurement reference voltage and the band-gap reference voltage in response to the measurement reference voltage deviating from the second predetermined range; and a bias voltage monitor circuit configured to activate the third flag signal based on the bias voltage and the measurement reference voltage in response to the bias voltage deviating from the third predetermined range.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 10908028 Kwon Abstract, Provided herein may be a temperature sensing circuit and a semiconductor device having the same. The temperature sensing circuit may include an analog voltage generation circuit configured to convert a temperature into a voltage and output a temperature voltage, an analog-digital converter configured to convert the temperature voltage into a digital code, and a compensation circuit configured to adjust the digital code and then output an operation code to remove noise from the temperature voltage.
US 10359469 Jin; Xiankun para. (15) In applications where the value of a bandgap voltage reference that is supposed to be stable with temperature, the temperature sensor 27B may be used by the BIST controller 26 to detect temperature changes so that the BIST analyzer 25 can calculate what the corresponding voltage reference output should be. In addition, the BIST controller 26 can use the voltage sensor 27C to measure the actual voltage reference output to see whether or not it is within the specified tolerance. If not, the BIST controller 26 and BIST analyzer 25 could trim or adjust the voltage reference until it is within the specified tolerance.
Conclusion
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: March 31, 2026
Non-Final Rejection 20260325
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV