Prosecution Insights
Last updated: October 02, 2026
Application No. 18/955,036

AMPLIFIER CIRCUIT

Non-Final OA §103
Filed
Nov 21, 2024
Priority
Dec 22, 2023 — TW 112150201
Examiner
KINKEAD, ARNOLD M
Art Unit
Tech Center
Assignee
Silicon Integrated Systems Corp.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1280 granted / 1403 resolved
+31.2% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
14 currently pending
Career history
1414
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
41.6%
+1.6% vs TC avg
§102
30.8%
-9.2% vs TC avg
§112
18.1%
-21.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1403 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Please provide a translation of the Foreign Priority Document. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1 ,5 ,7, 9, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karki( Fully differential amplifiers remove noise from common-mode signals EDN,November 9, 2000) in view of Kulej et al.( 0.5 V Multiple-Input Fully Differential Operational Transconductance Amplifier and Its Application to a Fifth-Order Chebyshev Low-Pass Filter for Bio- Signal Processingl, MDPI, 2024). Re claim 1: The reference to Karki, see figure below, shows a programmable gain amplifier circuit(a function of Vcm), having a 2nd positive(IN+) input terminal, a first negative(IN-) input terminal, a positive(OUT+) output terminal and a negative output(OUT-) terminal; a first resistor(top R2) connected between the first negative input terminal and the positive output terminal; a second resistor having one terminal connected to the first negative input (1st IN-)terminal and the first resistor, and another terminal connected to the second positive(2nd IN+) input terminal; and at least one third resistor(bottom R2)connected between the second positive input terminal and the negative output terminal, wherein a sum of resistances of the first resistor and the second resistor is same as a resistance of the at least one third resistor. PNG media_image1.png 516 1004 media_image1.png Greyscale The reference to Karki does not show additional inputs(+/-), such as another positive input terminal, another negative input terminal, however, multiple input fully differential configurations is conventional and as noted below in the reference to Kulej et al, adds flexibility and a more compact design approach to certain implementations as noted. Please note 1st Res + 2nd Res= 3rd Res, as 2nd Res=0 ohms. PNG media_image2.png 486 722 media_image2.png Greyscale In light of the above it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have recognized that the apparatus as described by Karki for the full differential amp with feedback, may be enhanced by way of additional inputs, as shown in Kulej et al, to allow for a more versatile topology as noted above while maintaining the benefits of the feedback paths, a simple matter of design consideration. Re claim 5: per main reference. a first capacitor (C1 top feedback path), wherein one terminal of the first capacitor is connected to the positive output(OUT+) terminal and another terminal of the first capacitor is connected to the first negative (1st IN-)input terminal. Re claim 7: per main reference. a second capacitor(C1 bottom feedback path), wherein one terminal of the second capacitor is connected to the negative output(OUT-) terminal and another terminal of the second capacitor is connected to the second positive (2nd IN+)input terminal. Re claim 9:per main reference. A first capacitor (C1 top feedback path)and a second capacitor(C1 bottom feedback path), wherein one terminal of the first capacitor is connected to the positive output terminal, another terminal of the first capacitor is connected to the first negative (1st IN-)input terminal, one terminal of the second capacitor is connected to the negative output (OUT+)terminal, and another terminal of the second capacitor is connected to the second positive(2nd IN+) input terminal. Re claim 11:per main reference. The first capacitor(C1 top) and the second capacitor (C1 bottom)have a same capacitance, as labeled(C1=C1). Allowable Subject Matter Claims 2-4, 6, 8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art cited on the PTOL-892 show differential amplifiers with elements of the general concepts such as the feedback, the variable gain and/or the multiple inputs. They do not suggest the resistances(sum of) as claimed in addition to all else claimed together. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARNOLD M KINKEAD/Primary Examiner, Art Unit 2836
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Prosecution Timeline

Nov 21, 2024
Application Filed
Sep 25, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+7.8%)
2y 0m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1403 resolved cases by this examiner. Grant probability derived from career allowance rate.

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