Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 8-18 and 21-29 (newly added) are presented for examination.
Election/Restriction
3. Applicant’s election without traverse of Species 2 (claims 8-18) is acknowledged.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 8-12, 21-24 and 28- are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-4, 10-11 or 15 of U.S. Patent No. 11756640. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 8-12 of the examined application are anticipated and the same scope of invention by claims 1-4, 10-11 or 15 of the reference such as a memory device, comprising: memory device, comprising: a plurality of first interconnect structures disposed in a first metallization layer of a plurality of metallization layers over a substrate; a plurality of access transistors disposed over the first metallization layer;
The claim 1 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a sense amplifier including a plurality of sense amplifier transistors formed on the substrate while in the reference claimed silence. However, a paragraph 30 of Young et al. US Pub. No. 20210408021 discloses the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry. The devices formed on the top surface of the semiconductor material layer 9.
Claims 13-18 are rejected due to the rejection of the parent claim.
Claims 21 and 24 of the examined application are anticipated and the same scope of invention by claims 1-4, 10-11 or 15 of the reference such as a memory device, comprising: a plurality of interconnect structures disposed in a metallization layer over a substrate; and a plurality of access transistors disposed over the metallization layer, wherein each of the plurality of interconnect structures is coupled to a corresponding one of the plurality of access transistors in series, operatively serving as a respective one of a plurality of one-time programmable electrical fuses.
Claims 22-23 are obvious to a paragraph 30 of Young et al. US Pub. No. 20210408021 discloses the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry. The devices formed on the top surface of the semiconductor material layer 9.
Claims 25-27 are rejected due to the rejection of the parent claim.
Claim 28 of the examined application are anticipated and the same scope of invention by claims 1-4, 10-11 or 15 of the reference such as a method, comprising: forming a plurality of first interconnect structures disposed on a first metallization layer; and forming a plurality of access transistors over the first metallization layer and respectively coupled to the plurality of first interconnect structures.
Claim 29 is rejected due to the rejection of the parent claim.
6. Claims 8-12, 21-24 and 28 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2, 5, 8-9 and 12-13, or 15-19 of U.S. Patent No. 12176049. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 8-12 of the examined application are anticipated and the same scope of invention by claims 1-2, 5, 8-9 and 12-13, or 15-19 of the reference such as a memory device, comprising: memory device, comprising: a plurality of first interconnect structures disposed in a first metallization layer of a plurality of metallization layers over a substrate; a plurality of access transistors disposed over the first metallization layer;
The claim 1 of examined application are obvious over the claim 1 of reference because the claim seems to differ because the claim seems to differ from the reference in that the claimed invention of the examined application recites a sense amplifier including a plurality of sense amplifier transistors formed on the substrate while in the reference claimed silence but it should be inherent in the memory device in order to sense a data read from the accessed memory cell, see 332 and 334 in Fig. 3A for the sense amplifiers. Also see a paragraph 30 of Young et al. US Pub. No. 20210408021 that discloses the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry. The devices formed on the top surface of the semiconductor material layer 9.
Claims 13-18 are rejected due to the rejection of the parent claim.
Claims 21 and 24 of the examined application are anticipated and the same scope of invention by claims 1-2, 5, 8-9 and 12-13, or 15-19 of the reference such as a memory device, comprising: a plurality of interconnect structures disposed in a metallization layer over a substrate; and a plurality of access transistors disposed over the metallization layer, wherein each of the plurality of interconnect structures is coupled to a corresponding one of the plurality of access transistors in series, operatively serving as a respective one of a plurality of one-time programmable electrical fuses.
Claims 22-23 are inherent or obvious about the sensor amplifier. It should be inherent in the memory device in order to sense a data read from the accessed memory cell, see 332 and 334 in Fig. 3A for the sense amplifiers. Also see a paragraph 30 of Young et al. US Pub. No. 20210408021 that discloses the devices in the peripheral region may include a sensing circuitry and/or a programming circuitry. The devices formed on the top surface of the semiconductor material layer 9.Claims 25-27 are rejected due to the rejection of the parent claim.
Claim 28 of the examined application are anticipated and the same scope of invention by claims 1-2, 5, 8-9 and 12-13, or 15-19 of the reference such as a method, comprising: forming a plurality of first interconnect structures disposed on a first metallization layer; and forming a plurality of access transistors over the first metallization layer and respectively coupled to the plurality of first interconnect structures.
Claim 29 is rejected due to the rejection of the parent claim.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
9. Claims 8-12, 21-24 and 28 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Omid-Zohoor et al. US Pub. No. 20180019018 (IDS)
As per claims 8-10, 12, 21-23 and 28, Fig. 6 of Omid-Zohoor is directed to a memory device, comprising: a plurality of first interconnect structures (stacks of vias and two or more metal layers, par. 62) disposed in a first metallization layer (metal 1 layer) of a plurality of metallization layers (par. 62) over a substrate (par. 24); a plurality of access transistors (612s, par. 616) disposed over the first metallization layer; a sense amplifier (sense circuitry, par. 13) including a plurality of sense amplifier transistors (inherent in the sense amplifier) formed on the substrate; and wherein each of the plurality of first interconnect structures is coupled to a corresponding one of the plurality of access transistors in series (Fig. 6 and par. 62), operatively serving as a respective one of a plurality of one-time programmable electrical fuses (616, pars. 24 and 61).
As per claim 11, a paragraph 62 of Omid-Zohoor discloses further comprising a plurality of fuse resistors (616s) disposed over the first metallization layer.
As per claim 24, a paragraph 62 of Omid-Zohoor discloses further comprising a plurality of second interconnect structures between the substrate and the plurality of access transistors.
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
11. Claims 8 -9, 21-24, and 28 are rejected under 35 U.S.C. § 103(a) as being unpatentable Young et al. US Pub. No. 20210408021 (IDS) in view of Lee et al. US Pub. No. 20200335141 IDS).
As per claims 8 -9, 21-23, and 28, Fig. 13 of Young discloses a memory device, comprising: a plurality of first interconnect structures (648, 642, 190 and 180, par. 92) disposed in a first metallization layer (648) of a plurality of metallization layers over a substrate (8, par. 24); a plurality of access transistors (801, par. 54 or 110 and 91) disposed over the first metallization layer; a sense amplifier including a plurality of sense amplifier transistors formed on the substrate (par. 30); and wherein each of the plurality of first interconnect structures is coupled to a corresponding one of the plurality of access transistors in series (Fig. 13)
The abstract of Young discloses the ferroelectric memory cells but fails to disclose a plurality of one-time programmable electrical fuses. However, paragraph 34 of Lee discloses the one-time programmable electrical fuses may be used the ferroelectric memory cells. Therefore, it would have been obvious to a person of ordinary skill in the art at the time invention was made to use Young’s ferroelectric memory cells to become the one-time programmable electrical fuses as taught by Lee in order to use the ferroelectric memory cells as the one-time programmable electrical fuses (par. 34).
As per claim 24, Fig. 13 of Young discloses further comprising a plurality of second interconnect structures between the substrate and the plurality of access transistors.
12. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
13. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HOAI V HO/Primary Examiner, Art Unit 2827
Prosecution Insights