Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed May 20th, 2026 has been entered. Claims 1, 3-10, 13-17 and 20 are pending in this application. Applicant amended independent claims 1, 10, and 17 to further teach that the first test corresponds to a structural test of an integrated circuit and the second test corresponds to a functional test of an integrated circuit. Claims 2, 11-12, and 18-19 have been canceled.
The amendment has been fully considered but is not sufficient to overcome the outstanding rejection. In light of the amendments, the rejection made under 35 USC § 103 has been modified to additionally rely on Sul (US 7,840,861) for the newly added limitations. See the updated rejection below.
Response to Arguments
Applicant's arguments filed May 20th, 2026 have been fully considered but they are not persuasive.
While the previously applied references teach the claimed segmented scan chain architecture and selective routing of scan data, the rejection has been modified to additionally rely on Sul for the limitation that the first test corresponds to a structural test of an integrated circuit and the second test corresponds to a functional test of an integrated circuit. Sul teaches scan-based structural testing together with at-speed functional testing of an integrated circuit. Therefore, the combination of Mittal, in view of Shah, and further in view of Sul teaches or suggests the amended limitations. Accordingly, the rejection is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 10, 13-14, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mittal et al. (US 2016/0266202), hereinafter Mittal, in view of Shah et al. (US 2019/0011500), hereinafter Shah, and further in view of Sul (US 7,840,861).
Regarding claim 1, Mittal teaches an apparatus (Mittal, Fig. 1) comprising:
a test controller (Mittal, Fig. 1, scan controller 130);
a scan chain coupled to the test controller (Mittal, para. [0021], lines 1-3, "FIG. 1 illustrates a simplified view of a scan architecture that illustrates how a circuit 100 may be configured into a scan chain during test"), the scan chain including a first segment and a second segment (Mittal, Fig. 5, segments 501 & 502, para. [0039], lines 1-2, "In this example, scan chain 104 is divided into segments 501, 502").
Mittal fails to teach circuitry coupled to the test controller and the scan chain, the circuitry configured to provide, to the second segment, an output of the first segment in connection with a first test, the circuitry further configured to provide, to the second segment, a test pattern in connection with a second test, wherein the first test corresponds to a structural test of an integrated circuit, and wherein the second test corresponds to a functional test of the integrated circuit.
However, Shah, in an analogous art, teaches circuitry coupled to the test controller and the scan chain, the circuitry configured to provide, to the second segment, an output of the first segment in connection with a first test (Shah et al. (US 2019/0011500), para. [0003], lines 3-7, "According to one implementation, a scan chain includes a first segment of scan-flops connected in series with a second segment of scan-flops and the second segment is configured to receive an output from the first segment"), the circuitry further configured to provide, to the second segment, a test pattern in connection with a second test (Shah, para. [0003], lines 7-11, "A first multiplexor is positioned between the first segment and the second segment and configured to selectively supply test controller input to the second segment while preventing the second segment from receiving an output of the first segment"; the test controller input equates to a test pattern).
Mittal and Shah are both considered to be analogous to the claimed invention because both are in the same field of scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Mittal to incorporate the teachings of Shah by including the functionality of circuitry that provides an output of a first segment in connection with a first test and a test pattern in connection with a second test, to a second segment.
The suggestion/motivation for doing so would be to allow for different testing modes and enabling control of the scan chain during testing.
The combination of Mittal in view of Shah, taken singly or combined, fail to teach wherein the first test corresponds to a structural test of an integrated circuit, and wherein the second test corresponds to a functional test of the integrated circuit.
However, Sul, in an analogous art, teaches wherein the first test corresponds to a structural test of an integrated circuit, and wherein the second test corresponds to a functional test of the integrated circuit (Sul, Fig. 2 teaches a “SCAN MODE” followed by an “AT-SPEED FUNCTIONAL TEST MODE”; col. 8, lines 33-38, “Programmable test clock controller 800 is configured to generate configurable test clocks for structural delay tests using a relatively low-speed scan clock [i.e., at "scan speed"] and a relatively high-speed functional clock [i.e., "at speed"] to configure a test clock 830 to implement multiple delay test protocols”).
Mittal, Shah, and Sul are considered to be analogous to the claimed invention because they are in the same field of scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah to incorporate the teachings of Sul by including the functionality of performing both structural scan testing and functional testing.
The suggestion/motivation for doing so would be to validate both the structural integrity and functional operation of the integrated circuit.
Regarding claim 3, the combination of Mittal in view of Shah, further in view of Sul, teaches the apparatus of claim 1, wherein the first test is associated with a first length of the scan chain, and wherein the second test is associated with a second length of the scan chain, the second length less than the first length (Shah, para. [0019], lines 2-10, "the scan chain 110 includes circuitry components that facilitate selective, isolated testing of individual segments of the scan chain 110 such that one portion of the scan chain 110 can be tested without causing any toggling in another portion of the scan chain 110. In another implementation, the scan chain 110 includes circuitry components that facilitate selective testing of individual chains within a functional block in isolation from one another. Both of these solutions reduce power draw and simplify debugging"; teaches testing individual segments of the scan chain independently, and allowing one portion of the scan chain to be tested in isolation; this implies different scan chain lengths, with a full scan chain having the longer length, and the isolated segment having the shorter length).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Mittal to incorporate the teachings of Shah by including the functionality of testing modes based on the scan chain’s length.
The suggestion/motivation for doing so would be to allow for different testing modes and enabling control of the scan chain during testing.
Regarding claim 4, the combination of Mittal in view of Shah, further in view of Sul, teaches the apparatus of claim 1, wherein the circuitry includes a plurality of multiplexers (MUXes) (Mittal, Fig. 10 & Fig. 11 teach multiple multiplexers).
Regarding claim 10, Mittal teaches a method comprising:
initiating a test associated with a scan chain of an integrated circuit (Mittal, Fig. 12, blocks 1202), the scan chain including a first segment and a second segment (Mittal, Fig. 12, blocks 1204).
Mittal fails to teach during the test, selecting, as an input to the second segment, one of an output of the first segment or a test pattern that is input to the first segment; wherein the selected input to the second segment corresponds to the output of the first segment based on the test corresponding to a structural test of the integrated circuit, and wherein the selected input to the second segment corresponds to the test pattern based on the test corresponding to a functional test of the integrated circuit; and receiving a test result associated with the scan chain, the test result based on the selected input to the second segment.
However, Shah teaches during the test, selecting, as an input to the second segment, one of an output of the first segment (Shah, para. [0003], lines 3-7, "According to one implementation, a scan chain includes a first segment of scan-flops connected in series with a second segment of scan-flops and the second segment is configured to receive an output from the first segment") or a test pattern that is input to the first segment (Shah, para. [0003], lines 7-11, "A first multiplexor is positioned between the first segment and the second segment and configured to selectively supply test controller input to the second segment while preventing the second segment from receiving an output of the first segment"; the test controller input equates to a test pattern); and receiving a test result associated with the scan chain (Shah, para. [0014], lines 2-7, "During a test sequence referred to herein as "scan chain testing," the test controller 112 selects test scan patterns 114 and transmits control signals to the user function block 104 for selectively programming (loading) individual elements of the scan chain 110 with values of each selected test scan pattern"; the scan chain values equate to test results), the test result based on the selected input to the second segment (Shah, para. [0013] through [0016] teaches selected inputs controlling what data becomes input of the second segment, the data moving through the scan chain, and the captured scan chain values becoming test output).
Mittal and Shah are both considered to be analogous to the claimed invention because both are in the same field of scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Mittal to incorporate the teachings of Shah by including the functionality of selecting an output or a test pattern of a first segment, as an input to a second segment, and receiving a test result based on the selected input to the second segment.
The suggestion/motivation for doing so would be to allow for different testing modes and enabling control of the scan chain during testing.
The combination of Mittal in view of Shah, taken singly or combined, fail to teach wherein the selected input to the second segment corresponds to the output of the first segment based on the test corresponding to a structural test of the integrated circuit, and wherein the selected input to the second segment corresponds to the test pattern based on the test corresponding to a functional test of the integrated circuit.
However, Sul, in an analogous art, teaches wherein the selected input to the second segment corresponds to the output of the first segment based on the test corresponding to a structural test of the integrated circuit, and wherein the selected input to the second segment corresponds to the test pattern based on the test corresponding to a functional test of the integrated circuit; (Sul, Fig. 2 teaches a “SCAN MODE” followed by an “AT-SPEED FUNCTIONAL TEST MODE”; col. 8, lines 33-38, “Programmable test clock controller 800 is configured to generate configurable test clocks for structural delay tests using a relatively low-speed scan clock [i.e., at "scan speed"] and a relatively high-speed functional clock [i.e., "at speed"] to configure a test clock 830 to implement multiple delay test protocols”).
Mittal, Shah, and Sul are considered to be analogous to the claimed invention because they are in the same field of scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah to incorporate the teachings of Sul by including the functionality of performing both structural scan testing and functional testing.
The suggestion/motivation for doing so would be to validate both the structural integrity and functional operation of the integrated circuit.
Claim 13 is a method with limitations similar to the apparatus of claim 3, and is rejected under the same rationale.
Regarding claim 14, the combination of Mittal in view of Shah, further in view of Sul, teaches the method of claim 10, wherein selecting the input to the second segment includes providing a control signal to a multiplexer (MUX) that is coupled to the first segment and to the second segment (Mittal, Fig. 10 & Fig. 11 teach multiple multiplexers).
Claim 17 is a non-transitory computer-readable medium with limitations similar to the method of claim 10, and is rejected under the same rationale.
Claim 20 is a non-transitory computer-readable medium with limitations similar to the apparatus of claim 3, and is rejected under the same rationale.
Claims 5-9 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mittal in view of Shah, further in view of Sul, as applied to claim 1 above, and further in view of Agashe et al. (US 7,134,061), hereinafter Agashe.
Regarding claim 5, the combination of Mittal in view of Shah, further in view of Sul, teaches the apparatus of claim 1, but fails to teach further comprising an exclusive-OR (XOR) gate coupled to an output of the second segment.
However, Agashe, in an analogous art, teaches further comprising an exclusive-OR (XOR) gate coupled to an output of the second segment (Agashe, Fig. 9 teaches multiple signals being combined through XOR gates to produce output signals).
Mittal, Shah, and Agashe are considered to be analogous to the claimed invention because they are in the same field of scan testing.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah, further in view of Sul, to incorporate the teachings of Agashe by including the functionality of an XOR gate.
The suggestion/motivation for doing so would be to combine various inputs to generate an output.
Regarding claim 6, the combination of Mittal in view of Shah, further in view of Sul, and further in view of Agashe teaches the apparatus of claim 5, wherein the XOR gate includes:
a first input coupled to a first output of the first segment and configured to receive a first result from the first segment (Agashe, Fig. 1A, scan chain A output1);
a second input coupled to a second output of the second segment and configured to receive a second result from the second segment (Agashe, Fig. 1A, scan chain B output2); and
an output configured to perform an XOR operation based on the first result and the second result to generate a test result associated with the scan chain (Agashe, Fig. 1A, TM output signals).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah, further in view of Sul, to incorporate the teachings of Agashe by including the functionality of an output being configured to generate a scan chain test result based on a first and second result from respective segments.
The suggestion/motivation for doing so would be to allow for a high performing, cost effective scan test circuitry (Agashe, col. 11, lines 32-34, “Advantages of this design include but are not limited to a scan test circuitry having a high performance, simple, and cost effective design”).
Regarding claim 7, the combination of Mittal in view of Shah, further in view of Sul, and further in view of Agashe teaches the apparatus of claim 1, wherein the circuitry includes a control circuit that includes:
a first input coupled to a first output of the first segment (Agashe, Fig. 1A, scan chain A output1);
a second input coupled to at least one other output of at least one other first segment in another scan chain (Agashe, Fig. 1A, scan chain B output2); and
an output configured to output test data associated with the first segment and the at least one other first segment (Agashe, Fig. 1A, TM output signals).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah, further in view of Sul, to incorporate the teachings of Agashe by including the functionality of an output being configured to generate a scan chain test result based on a first and second result from respective segments.
The suggestion/motivation for doing so would be to allow for a high performing, cost effective scan test circuitry (Agashe, col. 11, lines 32-34, “Advantages of this design include but are not limited to a scan test circuitry having a high performance, simple, and cost effective design”).
Regarding claim 8, the combination of Mittal in view of Shah, further in view of Sul, and further in view of Agashe teaches the apparatus of claim 7, wherein the control circuit corresponds to an internal test (INTEST) multiple input signature register (MISR) (Agashe, col. 1, lines 60-63, "Additional internal embedded test circuitry such as scan chain circuitry may also be added to the design to increase the internal testability of internal sequential designs").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah, further in view of Sul, to incorporate the teachings of Agashe by including the functionality of an INTEST MISR.
The suggestion/motivation for doing so would be to increase internal testability (Agashe, col. 1, lines 60-63, "Additional internal embedded test circuitry such as scan chain circuitry may also be added to the design to increase the internal testability of internal sequential designs").
Regarding claim 9, the combination of Mittal in view of Shah, further in view of Sul, and further in view of Agashe teaches the apparatus of claim 7, wherein the control circuit corresponds to an external test (EXTEST) multiple input signature register (MISR) (Mittal, para. [0037], lines 5-10, "Decompressor logic 531 receives a stream of data and control signals from an external test system, such as tester 110 in FIG. 1 and separates the stream into the different data and control paths 112, 114, and 118 illustrated in FIG. 1, based on the test protocol supported by test port 130").
Regarding claim 15, the combination of Mittal in view of Shah, further in view of Sul, and further in view of Agashe teaches the method of claim 10, further comprising performing an exclusive-OR (XOR) operation to generate the test result based on a first result from the first segment and further based on a second result from the second segment (Agashe, Fig. 9 teaches multiple signals being combined through XOR gates to produce output signals).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah, further in view of Sul, to incorporate the teachings of Agashe by including the functionality of an XOR gate.
The suggestion/motivation for doing so would be to combine various inputs to generate an output.
Regarding claim 16, the combination of Mittal in view of Shah, further in view of Sul, and further in view of Agashe teaches the method of claim 10, further comprising:
providing the output of the first segment to one of a first internal test (INTEST) multiple input signature register (MISR) or to a first external test (EXTEST) MISR (Agashe, col. 1, lines 60-63, "Additional internal embedded test circuitry such as scan chain circuitry may also be added to the design to increase the internal testability of internal sequential designs"); and providing a second output of the second segment to one or more of a second INTEST MISR or a second EXTEST MISR (Mittal, para. [0037], lines 5-10, "Decompressor logic 531 receives a stream of data and control signals from an external test system, such as tester 110 in FIG. 1 and separates the stream into the different data and control paths 112, 114, and 118 illustrated in FIG. 1, based on the test protocol supported by test port 130").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Mittal in view of Shah, further in view of Sul, to incorporate the teachings of Agashe by including the functionality of an INTEST MISR.
The suggestion/motivation for doing so would be to increase internal testability (Agashe, col. 1, lines 60-63, "Additional internal embedded test circuitry such as scan chain circuitry may also be added to the design to increase the internal testability of internal sequential designs").
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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