DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,184,059. Although the claims at issue are not identical, they are not patentably distinct from each other because differences between the two sets of claims are only minor variations in recited scope or variations in the distribution of features between the independent and dependent claims that are not seen to involve an inventive step when the abilities of persons of ordinary skill are taken into full consideration.
Instant claim 1 recites: A method for testing a power system comprising: receiving a first test signal at a test terminal of a gate driver to begin a first test of a two-test protocol; configuring, during the first test, a power transistor in an OFF condition; decoupling a first input of a comparator of a current-sense fault detection circuit from a current sense terminal of the gate driver and coupling a test voltage to the first input, a second input of the comparator being coupled to a threshold voltage; and determining a passing first test or a failing first test based on an output of the comparator.
Patent claim 10 recites: A method for testing a power system comprising, the method comprising: receiving a first test signal at a test terminal of a gate driver to begin a first test; configuring, during the first test, a power transistor in an OFF condition; charging, by a desaturation fault detection circuit of the gate driver, a voltage of a blanking capacitor, the blanking capacitor coupled externally to the gate driver at a desaturation terminal of the gate driver; comparing, by the desaturation fault detection circuit, the voltage of the blanking capacitor to a threshold to generate a fault signal; and transmitting, by the desaturation fault detection circuit, a fault signal to a fault terminal of the gate driver when the voltage of the blanking capacitor exceeds the threshold determining that the first test has passed or failed based on the fault signal: and performing a second test based on the first test being passed, the second test including: configuring, during the second test, the power transistor in an ON condition.
The desaturation fault detection circuit is understood to include a comparator circuit because a voltage must be measured to determine the saturation of a driven transistor (saturation=transistor completely turned on by a drive signal voltage).
Instant claim 7 recites: A gate driver comprising: a driver circuit configured to drive a power transistor coupled to the gate driver in an OFF condition in response to a first test, and in an ON condition in response to a second test; and a current-sense fault detection circuit including: a current-sense switch being in an OFF condition based on the first test and in an ON condition based on the second test; a test switch being in an ON condition based on the first test and in an OFF condition based on the second test; and a comparator having a first input coupled to the test switch and the current-sense switch and having a second input coupled to a threshold voltage.
Patent claim 18 recites: A gate driver comprising: a driver circuit configured to_ generate an output signal at an output terminal of the gate driver to control an ON/OFF condition of a power transistor according to an input signal at an input terminal of the gate driver; and drive a power transistor coupled to the gate driver in an OFF condition in response to a first test signal; and drive the power transistor coupled to the gate driver in an ON condition in response to a second test signal; and a desaturation fault detection circuit configured, upon receiving a test signal at a test terminal of the gate driver, to: disable a desaturation switch coupled between a desaturation terminal of the gate driver and a ground so that a current source of the desaturation fault detection circuit can charge a voltage of a blanking capacitor that is coupled externally to the gate driver at the desaturation terminal; receive the voltage of the blanking capacitor at a first input of a comparator coupled to the desaturation terminal, the comparator having a second input coupled to a threshold voltage; and transmit a fault signal to a fault terminal of the gate driver in response to the voltage of the blanking capacitor exceeding the threshold voltage, the fault signal indicating that the desaturation fault detection circuit is functioning properly charge, in response to the first test signal, a blanking capacitor coupled to a desaturation terminal of the gate driver; detect, during a first test period, that a voltage of the blanking capacitor satisfies a fault condition to determine that the blanking capacitor is operating properly; not charge, in response to the second test signal, the blanking capacitor; and detect, during a second test period, that the voltage of the blanking capacitor does not satisfy the fault condition to determine that the power transistor is operating properly.
Removal of the design considerations related to the connection and function of the capacitor blanking circuit is a simplification that would not involve an inventive step beyond the abilities of persons of ordinary skill in the art.
Instant claim 17 recites: A power system comprising: a power transistor coupled to a current-sense resistor, the current-sense resistor configured to generate a voltage corresponding to a current flowing through the power transistor; a current-sense filter coupled to the current-sense resistor; a gate driver including a current-sense fault detection circuit coupled to the current-sense filter at a current-sense terminal; and a control module configured to: perform a first test of the power system, the first test including: configuring the power transistor in an OFF condition; decoupling the current-sense fault detection circuit from the current-sense terminal; and configuring the current-sense fault detection circuit to compare a test voltage to a reference voltage; determine that the first test has passed or failed; and perform a second test of the power system after the first test has passed, the second test including: configuring the power transistor in an ON condition; coupling the current-sense fault detection circuit to the current-sense terminal to receive the voltage; and configuring the current-sense fault detection circuit to compare the voltage to the reference voltage.
Patent claim 1 recites: A power system comprising: a power transistor that is configurable in an ON condition or an OFF condition corresponding to a signal at a gate of the power transistor; a desaturation sense circuit coupled to a terminal of the power transistor and including a blanking capacitor configured to be charged to a voltage corresponding to a desaturation condition of the power transistor; a gate driver including: a driver circuit configured to generate the signal at the gate of the power transistor according to an input signal at an input terminal of the gate driver; and a desaturation fault detection circuit that is configured to receive the voltage of the blanking capacitor and generate a fault signal when the voltage of the blanking capacitor exceeds a threshold; and a control module configured to perform a first test of the power system, the first test including: transmitting a first test signal to a test terminal of the gate driver to configure the power transistor in the OFF condition and to configure the desaturation fault detection circuit to receive the voltage of the blanking capacitor, the voltage of the blanking capacitor charged by the desaturation fault detection circuit during the first test, determine that the first test has passed or failed: and perform a second test of the power system after the first test has passed, the second test including: transmitting a second test signal to the input terminal of the gate driver to configure the power transistor in the ON condition, the voltage of the blanking capacitor being charged by the power transistor in the ON condition.
Removal of the design considerations related to the connection and function of the capacitor blanking circuit is a simplification that would not involve an inventive step beyond the abilities of persons of ordinary skill in the art.
Instant dependent claims 2-6,8-16 and 18-20 recite features that are not seen to involve an inventive step in comparison to the features recited in dependent claims 2-9,11-17 and 19 of the patent. For example instant claim 2 recites features related to the control of a second test based on the result of the first test and patent claim 11 specifically recites “performing a second test based on the first test being passed”. Instant dependent claim 18 recites the use of an IGBT transistor, which is a feature recited in patent claim 7.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN W JACKSON whose telephone number is (571)272-2051. The examiner can normally be reached M-F 6:30-3:00.
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SWJackson
September 4, 2026
/STEPHEN W JACKSON/Primary Examiner, Art Unit 2838
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