DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 3 is objected to because of the following informalities: The recitation “and configure to receive the frequency signal” in lines 3-4, should be corrected to “and configured to receive the frequency signal”. Similarly, the word “configure” in lines 8 and 11 should be corrected to “configured”.
Appropriate correction is required.
Claims 4-18 are also objected as they inherit the deficiency noted above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the US Patent US 11,573,263 by Deng et al., (Deng hereafter).
Regarding claim 1, Deng teaches, a process corner simulation system comprising:
a frequency generator (ring oscillator 300 shown in Figure 3) configured to generate a frequency signal;
a transistor sensitive circuit (voltage division detection circuit 62 in Fig. 6, which comprise a plurality of transistors and it’s thus, sensitive to their behavior; see col. 12, lines 11-12) coupled to the frequency generator and configured to receive the frequency signal; and
a process corner simulator (not shown simulator that performs the process corner detection method 400 in Figure 4, as explained in col. 5, lines 28-38) coupled to the transistor sensitive circuit and configured to receive at least one output signal generated from the transistor sensitive circuit (step S1; see col. 5, lines 30-34);
wherein the at least one output signal outputted from the transistor sensitive circuit comprises speed information and duty cycle information (the signal outputted by the oscillator and provided to the external testing device has an inherent frequency, period and duty cycle);
wherein the process corner simulator uses a plurality of process corner models for generating a plurality of simulation results corresponding to different process corners according to the at least one output signal (the process corner simulator determines the process corner of each type of transistor in the chip containing the ring oscillators based on standard oscillation periods and measured oscillation periods in the chip; col. 5, lines 35-38. The examiner equates the standard oscillation period and the measured oscillation period, which are used to determine the process corner of each type of transistor, to the recited “process corner models”).
Regarding claim 19, Deng teaches the frequency generator is a ring oscillator (col. 4, lines 46-47).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Deng in view of the US Patent US 7,382,147 by Cano et al., (Cano hereafter).
Regarding claim 2, Deng teaches the system of claim 1, wherein the frequency generator comprises:
an inverter chain (plurality of inverters 31)) comprising:
an input terminal (terminal inverter 31 in connected to the output of gate 32);
M inverters coupled in series (31); and
an output terminal (output of 31 connected to gate 32);
a NAND gate (32) comprising:
a first input terminal (lower input terminal of 32 connected to 31) coupled to the output terminal of the inverter chain;
a second input terminal (terminal receiving signal EN) configured to receive a switch signal (EN); and
an output terminal (output terminal of gate 320 coupled to the input terminal of the inverter chain; wherein M is a positive even number (there are six inverters shown).
Deng substantially teaches all of the claimed elements as discussed above, except that it doesn’t explicitly mention a frequency divider coupled to the first input terminal of the NAND gate and configured to output the frequency signal.
Cano teaches in Figures 9 and 10, a system for testing semiconductors on a chip including the use of ring oscillators (910) that output an oscillating signal to an external testing device (see col. 12, lines 25-27). Before the oscillating signal is provided to the external testing device, it undergoes frequency division (using the divider connected to multiplexer 905) to slow the signal (see col. 12, lines 15-17).
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of frequency dividers connected to the output of ring oscillators as taught by Cano, and include a frequency divider connected to the output of the oscillator in the system disclosed by Deng, in order to obtain a lower, more manageable frequency at the output, eliminating the need for specialized equipment to handle/process higher frequencies.
Claim 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Deng in view of the US Patent Application Publication PGPub 2017/0356811 by Kothandaraman et al., (Kothandaraman hereafter).
Regarding claim 20, Deng substantially teaches all of the recited elements as discussed above, except that Deng is silent about the corner simulator being coupled to a time-to-digital converter (TDC) configured to digitize the results generated by the process corner simulator.
However, the use of time-to-digital converters in applications such as high-speed measurements is well known in the art. For example, Kothandaraman discusses in paragraph 0038 the use of a time-to-digital converter to determine the difference between a first and second ring oscillator signals. It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of time-to-digital converters as taught by Kothandaraman, in process corner simulator disclosed by Deng, in order to obtain precise digital readings of time/period differences between oscillators, enhancing the process of identifying frequency/period differences between the ring oscillators.
Allowable Subject Matter
Claims 3-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of record doesn’t teach alone or in combination the process corner simulation circuit wherein the transistor sensitive circuit comprises a first buffer chain coupled to the frequency generator and configured to receive the frequency signal, and configured to generate a first buffer chain output signal according to the frequency signal; a second buffer chain coupled to the frequency generator and configured to receive the frequency signal, and configured to generate a second buffer chain output signal according to the frequency signal; and a third buffer chain coupled to the frequency generator and configured to receive the frequency signal, and configured to generate a third buffer chain output signal according to the frequency signal, in combination with all other elements recited.
As to claims 4-18, the claims are objected as they include the allowable subject matter in claim 3 noted above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- The US Patent US 10,527,667 by Huang et al.
- The US Patent Application Publication PGPub 2017/0219649 by Shan et al.
- the US Patent Application Publication PGPub 2017/0089974 by PU et al.
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/RICHARD ISLA/ Primary Patent Examiner, Art Unit 2858 October 13, 2026
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