Prosecution Insights
Last updated: August 17, 2026
Application No. 18/956,017

CONTACTLESS ELECTRICAL INSPECTION PROCESS

Non-Final OA §102§103
Filed
Nov 22, 2024
Examiner
HAWKINS, DOMINIC E
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
651 granted / 748 resolved
+19.0% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
16 currently pending
Career history
761
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
59.8%
+19.8% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
10.8%
-29.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 748 resolved cases

Office Action

§102 §103
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 of U.S. Application 18/956,017 filed on November 22, 2024 are presented for examination. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim 1 is rejected under 35 U.S.C. 102(a1) as being unpatentable over Kim et al (USPGPub 20240170445). Regarding claim 1, Kim discloses a method, comprising: providing a first electronic component (D1); providing a second electronic component (D2); performing a bonding process (using 60) to bond the first electronic component and the second electronic component (abstract discloses bonding the first and second dies to each other); and performing an inspection process (using 10) during or after the bonding process (par 41 discloses inspections after each bonding process), wherein the inspection process comprises a contactless inspection process (par 33-35 and par 40 discloses the inspection process using camera 40 in combination with heater 30 to contactless inspect the components). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (USPGPub 20240170445). Regarding claim 11, Kim discloses a method, comprising: providing a first electronic component (D1); providing a second electronic component (D2); performing a bonding process (using 60) to bond the first electronic component and the second electronic component(abstract discloses bonding the first and second dies to each other); and performing an inspection process (using 10) in a low-pressure environment during or after the bonding process(par 41 discloses inspections after each bonding process). Kim does not fully disclose wherein a gas pressure in the low-pressure environment is less than or approximately equal to 100Pa. However, It has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention taught by Kim to be limited to a gas pressure in the low-pressure environment is less than or approximately equal to 100Pa because it is known in semiconductors for contamination control and equipment protection). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (USPGPub 20240170445) in view of Yamamoto et al (USPGPub 20030129497). Regarding claim 12, Kim does not fully disclose wherein the inspection process is performed by an electronic beam inspection system. However, Yamamoto discloses wherein the inspection process is performed by an electronic beam inspection system (par 70 discloses electron beam inspection).It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Yamamoto in order to determine properties of the electronic component. Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (USPGPub 20240170445) in view of Li et al (USPGPub 20260005186). Regarding claim 15, Kim does not fully disclose wherein performing an inspection process to the first electronic component before performing the bonding process in the low-pressure environment. However, Li discloses performing an inspection process to the first electronic component before performing the bonding process in the low-pressure environment (par 43 discloses inspection and par 59 discloses bonding after inspection). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Li in order to determine properties of the electronic component. Regarding claim 16, Kim does not fully disclose wherein performing an inspection process to the second electronic component before performing the bonding process in the low-pressure environment. However, Li discloses performing an inspection process to the second electronic component before performing the bonding process in the low-pressure environment (par 43 discloses inspection and par 59 discloses bonding after inspection. Therefore, it inspects the second electronic before the bonding). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Kim in view of Li in order to determine properties of the electronic component. Allowable Subject Matter Claims 2-10, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 2, the prior art of record taken alone or in combination fail to teach or suggest a method, comprising: wherein: the first electronic component and the second electronic component are disposed face to face for performing the bonding process; the first electronic component comprises a first exposed conductor for the inspection process; and a distance between the first exposed conductor of the first electronic component and an edge of the second electronic component closest to the first exposed conductor is larger than or approximately equal to 200 µm in combination with the other limitations of the claim. Regarding claim 3, the prior art of record taken alone or in combination fail to teach or suggest a method, comprising: wherein the first electronic component comprises a plurality of first exposed conductors and a plurality of second exposed conductors, wherein: the second electronic component is disposed on at least two of the plurality of second exposed conductors for performing the bonding process; and the inspection process is performed by at least one of the plurality of first exposed conductors non-overlapped to the second electronic component in combination with the other limitations of the claim. Claims 4-10 are also objected as they depend on objected claim 3. Regarding claim 13, the prior art of record taken alone or in combination fail to teach or suggest a method, comprising: wherein the inspection process comprises directing an electron beam toward at least one conductive portion of the first electronic component or the second electronic component in combination with the other limitations of the claim. Claim 14 is also objected as it depends on objected claim 13. Reasons for Allowance Claims 17-20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 17, the prior art of record taken alone or in combination fail to teach or suggest a method, comprising: wherein the inspection process comprises determining an electrical property between a first conductor and a second conductor of the first electronic component or the second electronic component by an inspecting image corresponding to the second conductor in combination with the other limitations of the claim. Claims 18-20 are also allowed as they depend on allowed claim 17. Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pan et al (USPGPub 20260123527): discloses multiple semiconductors and bonding them to a substrate). Guo et al (USPGPub 20250076184): discloses inspecting the package after a bonding process. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOMINIC E HAWKINS whose telephone number is (571)272-2647. The examiner can normally be reached Monday-Friday 7:30am-5:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOMINIC E HAWKINS/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Nov 22, 2024
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+12.0%)
2y 2m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 748 resolved cases by this examiner. Grant probability derived from career allowance rate.

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