DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on May 8, 2026 has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-11 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 11,610,541 B1, IDS dated May 8, 2026).
As to claim 1, Kim discloses a pixel (Kim, FIG. 2, col. 8, l. 20, “pixel PX”) comprising:
a light emitting element (Kim, FIG. 2, col. 8, l. 27, “light emitting element LD”);
a first transistor (Kim, FIG. 2, col. 8, l. 29, “transistor T1”) including a gate electrode electrically connected to a first node (Kim, see FIG. 2, the gate electrode of “transistor T1” connected to “node N1”), a first electrode electrically connected to a second node (Kim, see FIG. 2, the source of “transistor T1” connected to “node N5”) to which a first power voltage (Kim, FIG. 2, col. 8, l. 39, “power VDD”) for driving the light emitting element (Kim, FIG. 2, col. 8, l. 27, “light emitting element LD”) is to be applied (Kim, see FIG. 2), and a second electrode electrically connected to the light emitting element (Kim, see FIG. 2, the drain of “transistor T1” connected to “light emitting element LD” via “transistor T7”); and
a bias control transistor (Kim, FIG. 2, col. 10, l. 42, “transistor T9”) including a gate electrode for receiving a bias control signal (Kim, see FIG. 2, the gate of “transistor T9” receiving “emission control signal” via “emission control line ELi”) supplied from an emission driving circuit (Kim, FIGS. 1-2, col. 4, l. 58, “emission driver 500”) and distinct from any scan signal (Kim, see FIGS. 1-2, col. 6, l. 19, e.g., scan signals via “scan lines SL1i, SL2i, and SL3i”) supplied from a scan driving circuit (Kim, FIGS. 1-2, e.g., col. 4, l. 58, “scan drivers 200, 300, and 400”), a first electrode electrically connected to the second node (Kim, see FIG. 2, the drain of “transistor T9” connected to “node N5”), and a second electrode electrically connected to a bias power line (Kim, see FIG. 2, col. 5, l. 6, the source of “transistor T9” connected to “power Vbs (or bias power)”), wherein the bias control transistor (Kim, FIG. 2, col. 10, l. 42, “transistor T9”) is configured to transmit a bias voltage (Kim, FIGS 1-2, col. 5, l. 43, “bias power Vbs may be power for supplying a predetermined on-bias voltage to a source electrode of the driving transistor”) received through the bias power line (Kim, see FIG. 2, col. 5, l. 6, “power Vbs (or bias power)”) to the second node (Kim, see FIG. 2, “node N5”).
As to claim 7, Kim discloses the pixel according to claim 1, further comprising:
a first capacitor (Kim, FIG. 2, col. 8, l. 26, “capacitor C2”) comprising a first electrode electrically connected to a fourth node (Kim, see FIG. 2, 1st electrode of “capacitor C2” connected to “node N3”) and a second electrode to which the first power voltage is applied (Kim, see FIG. 2, 2nd electrode of “capacitor C2” to which “power VDD” is applied); and
a second capacitor (Kim, FIG. 2, col. 8, l. 26, “capacitor C2”) comprising a first electrode electrically connected to the fourth node (Kim, see FIG. 2, 1st electrode of “capacitor C1” connected to “node N3”) and a second electrode electrically connected to the first node (Kim, see FIG. 2, 2nd electrode of “capacitor C1” connected to “node N1”).
As to claim 8, Kim discloses the pixel according to claim 7, further comprising:
a fifth transistor (Kim, FIG. 2, col. 9, ll. 39-50, “transistor T5”) to switch an electrical connection between a first power line (Kim, FIG. 2, col. 9, ll. 39-50, “reference power VREF”) to which a reference voltage is applied (Kim, see FIG. 2, col. 9, ll. 39-50, “voltage of the reference power VREF”) and the fourth node (Kim, see FIG. 2, “node N3”).
As to claim 9, Kim discloses the pixel according to claim 7, further comprising:
a first initialization transistor (Kim, FIG. 2, col. 9, ll. 27-38, “transistor T4”) to switch an electrical connection between a second power line (Kim, FIG. 2, col. 9, ll. 27-38, “initialization power Vint”) to which a first initialization voltage is applied (Kim, FIG. 2, col. 9, ll. 27-38, “the voltage of the initialization power Vint”) and the first node (Kim, see FIG. 2, “node N1”).
As to claim 10, Kim discloses the pixel according to claim 1, further comprising:
a second initialization transistor (Kim, FIG. 2, col. 10, ll. 22-41, “transistor T8”) to switch an electrical connection between a third power line (Kim, FIG. 2, col. 10, ll. 22-41, “anode initialization power Vaint”) to which a second initialization voltage is applied (Kim, FIG. 2, col. 10, ll. 22-41, “the voltage of the anode initialization power Vaint”) and the light emitting element (Kim, FIG. 2, col. 10, ll. 22-41, “light emitting element LD”).
As to claim 11, Kim discloses the pixel according to claim 1, the bias control signal (Kim, see FIG. 2, the “emission control signal” via “emission control line ELi”) is commonly applied to the gate electrode of the bias control transistor (Kim, see FIG. 2, the gate of “transistor T9”) and a gate electrode of the second initialization transistor (Kim, see FIG. 2, the gate of “transistor T8”).
As to claim 19, it differs from claim 1 only in that it is the electronic device comprising the pixels of claim 1. It recites substantially the same limitations as in claim 1, and further recites “a host system to output input image data corresponding to an image displayed during one frame period; and a display device to display the image based on the input image data”.
Kim discloses them, and further discloses a host system to output input image data corresponding to an image displayed during one frame period; and a display device to display the image based on the input image data (Kim, FIG. 1, col. 6, ll. 27-42, “timing controller 700 … in response to synchronization signals supplied from an outside source … may rearrange input image data supplied from the outside into image data RGB and supply the image data RGB to the data driver 600”; it is reasonably inferred that the “outside source” corresponds to a “host system”). Please see claim 1 for detailed analysis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4-6, 12-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 11,610,541 B1, IDS dated May 8, 2026) in view of In et al. (US 2021/0134210 A1).
As to claim 2, Kim does not explicitly teach the pixel according to claim 1, wherein in one frame period, a voltage level of the bias voltage to be applied to the second node increases.
However, In teaches the concept that in one frame period, a voltage level of the bias voltage to be applied to the second node increases (In, FIG. 8, [0190], “the voltage level of the bias power source Vbs may be increased corresponding to the repetition of the second period P2”).
At the time of effective filing date, it would have been obvious to one of ordinary skill in the art to modify the voltage level of the “predetermined on-bias voltage” via the “bias power Vbs” taught by Kim to be increased in one frame period including the “second period P2”, as taught by In, in order to provide “securing a threshold voltage compensation time of a first transistor of a pixel and periodically applying a bias voltage to the first transistor” (In, [0007]).
As to claim 4, Kim in view of In teaches the pixel according to claim 1, further comprising:
a scan transistor (Kim, FIG. 2, col. 9, ll. 1-10, “transistor T2”) including a gate electrode to which a scan signal is applied (Kim, FIG. 2, col. 9, ll. 1-10, “the gate electrode of the second transistor T2 may be connected to a first scan line SL1i to receive the first scan signal”), a first electrode electrically connected to a data line to which a data voltage is applied (Kim, FIG. 2, col. 9, ll. 1-10, source of “transistor T2” connected to “data line DLj”), and a second electrode electrically connected to a fourth node (Kim, FIG. 2, col. 9, ll. 1-10, drain of “transistor T2” connected to “node N3”), and
wherein one frame period comprises:
a data writing cycle in which the scan signal having a turn-on level is inputted to the second transistor and the light emitting element emits light based on the data voltage inputted in the data writing cycle (In, FIG. 3, [0115], “The first period P1 may include a period, in which a data signal DS substantially corresponding to an output image is written”; [0123], “each of the initialization period IP and the write period WP is a period in which the first scan signal is supplied, and may correspond to about one horizontal period”); and
a hold cycle in which the light emitting element emits light based on the data voltage inputted in the data writing cycle (In, FIG. 3, [0140], “The first transistor M1 controls an amount of driving current flowing through the light emitting device LD in accordance with the voltage of the second node N2. Then, the light emitting device LD generates light with a luminance corresponding to the amount of driving current during the emission period EP”). Examiner renders the same motivation as in claim 2.
As to claim 5, In teaches the pixel according to claim 1, further comprising:
a first emission control transistor (In, FIG. 2, [0103], “transistor M5”) electrically connected between (In, see FIG. 2) a first power line to which the first power voltage (In, FIG. 2, [0097], “first power source VDD”) is applied and the second node (In, FIG. 2, [0097], “node N1”); and
a second emission control transistor (In, FIG. 2, [0104], “transistor M6”) electrically connected between (In, see FIG. 2) a third node (In, FIG. 2, [0104], “node N3”) and the light emitting element (In, FIG. 2, [0095], “light emitting device LD”). Examiner renders the same motivation as in claim 2.
As to claim 6, In teaches the pixel according to claim 5, wherein the bias control transistor (In, FIG. 2, [0102], “transistor M4”) is turned on during at least a portion of a period during which the first light-emitting control transistor and the second light-emitting control transistor are turned off (In, FIG. 3, [0124]-[0126], “After the emission control signal is supplied to the emission control line Ei, the third scan signal may be supplied to the third scan line S3i during the first bias period BP1”; “In the first bias period BP1, the fourth transistor M4 and the eighth transistor M8 may be turned on in response to the third scan signal. When the fourth transistor M4 is turned on, a voltage of the bias power source Vbs may be supplied to the first node N1, and the first transistor M1 may be in an on-bias state (i.e., on-biased). Accordingly, the voltage of the bias power source Vbs having a constant value is supplied, and thus, a hysteresis characteristic of the first transistor M1 can be improved”). Examiner renders the same motivation as in claim 2.
As to claim 12, it differs from claim 1 only in that it is the display device comprising the pixel of claim 1. It recites substantially the same limitations as in claim 1, and further recites “a display device comprising: a display panel in which a plurality of pixels, a plurality of data lines electrically connected to the plurality of pixels, a plurality of scan lines electrically connected to the plurality of pixels, and a bias power line electrically connected to the plurality of pixels are disposed; a scan driving circuit configured to output, to the plurality of scan lines, a scan signal for controlling a timing at which the data voltage is inputted to the plurality of pixels; a data driving circuit configured to supply a data voltage to the plurality of data lines; and a power supply circuit configured to output the bias voltage to the bias power line”.
Kim teaches them, and further teaches a display device (Kim, FIG. 1, col. 4, ll. 56, “display device 1000”) comprising:
a display panel (Kim, FIG. 1, col. 4, ll. 56, “display panel 100”) in which a plurality of pixels (Kim, FIG. 1, col. 6, ll. 11, “pixel PX”), a plurality of data lines (Kim, FIG. 1, col. 6, ll. 12, “data lines DL”) electrically connected to the plurality of pixels (Kim, see FIG. 1, “DLj” connected to “PX”), a plurality of scan lines (Kim, FIG. 1, col. 6, ll. 12, “scan lines SL1, SL2, and SL3”) electrically connected to the plurality of pixels (Kim, see FIG. 1, “SL1i, SL2i, and SL3i” connected to “OX”), and a bias power line (Kim, FIGS. 1-2, col. 6, ll. 16, “bias power Vbs”) electrically connected to the plurality of pixels (Kim, see FIGS. 1-2, “Vbs” connected to “PX” via “T9”) are disposed (Kim, see FIGS. 1-2);
a scan driving circuit (Kim, FIG. 1, e.g., col. 4, ll. 57, “scan drivers 200, 300, and 400”) configured to output, to the plurality of scan lines (Kim, FIG. 1, col. 6, ll. 12, “scan lines SL1, SL2, and SL3”), a scan signal for controlling a timing at which the data voltage is inputted to the plurality of pixels (Kim, FIG. 1, e.g., col. 5, ll. 61, “an output frequency of the data driver 600 for one horizontal line (or pixel row) and/or an output frequency of the first scan driver 200 outputting a write scan signal may be determined in response to the image refresh rate”);
a data driving circuit (Kim, FIG. 1, col. 5, ll. 61, “data driver 600”) configured to supply a data voltage to the plurality of data lines (Kim, see FIGS. 1-2, supply data voltages via “data lines DL”).
Kim does not explicitly teach “a power supply circuit configured to output the bias voltage to the bias power line”.
However, In teaches a power supply circuit (In, FIG. 1, [0055], “power supply 800”) configured to output the bias voltage (In, FIG. 1, [0060], “voltage of a bias power source Vbs”) to the bias power line (In, FIG. 1, [0060], “bias power source Vbs”). Examiner renders the same motivation as in claim 2. Please also see claim 1 for detailed analysis.
As to claim 13, it recites substantially the same limitations as in claim 2, and In teaches them. Examiner renders the same motivation as in claim 2. Please see claim 2 for detailed analysis.
As to claim 14, In teaches the display device of claim 12, wherein one frame period (In, see FIG. 3) comprises:
a data writing cycle in which the scan driving circuit outputs the scan signal having a turn-on level to the plurality of scan lines, the data voltage is inputted to the plurality of pixels, and the light emitting element emits light based on the data voltage inputted to the plurality of pixels (In, FIG. 3, [0115], “The first period P1 may include a period, in which a data signal DS substantially corresponding to an output image is written”; [0123], “each of the initialization period IP and the write period WP is a period in which the first scan signal is supplied, and may correspond to about one horizontal period”); and a hold cycle in which the light emitting element emits light based on the data voltage inputted to the plurality of pixels in the data writing cycle (In, FIG. 3, [0140], “The first transistor M1 controls an amount of driving current flowing through the light emitting device LD in accordance with the voltage of the second node N2. Then, the light emitting device LD generates light with a luminance corresponding to the amount of driving current during the emission period EP”). Examiner renders the same motivation as in claim 2.
As to claim 20, it recites substantially the same limitations as in claim 2, and In teaches them. Examiner renders the same motivation as in claim 2. Please see claim 2 for detailed analysis.
Allowable Subject Matter
Claims 3 and 15-18 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 3, the closest known prior art, i.e., Kim et al. (US 11,610,541 B1, IDS dated May 8, 2026), Kim et al. (US 2023/0108865 A1), In et al. (US 2021/0134210 A1), Cho et al. (US 2021/0027719 A1, IDS), In et al. (US 2022/0301484 A1) and In et al. (US 2024/0105100 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein a peak voltage of the bias voltage is reduced over two or more frame periods”.
As to claim 15, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein, in a case where a total number of hold cycles increases to a preset number or more between two successive frames, the power supply circuit increases the voltage level of the bias voltage and outputs the bias voltage”.
As to claim 16, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein the bias voltage has one peak voltage, and wherein the peak voltage is a voltage level of the bias voltage to be outputted from the power supply circuit to a last hold cycle in the one frame”.
As to claim 17, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “wherein, as a frame is changed to another frame, the power supply circuit reduces a voltage level increment of the bias voltage and outputs the bias voltage”.
As to claim 18, it recites substantially the same limitations as in claim 3, and is allowable for the same reason above. Please see claim 3 for detailed analysis.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure: Kim et al. (US 2023/0108865 A1) is the PG-PUB of Kim et al. (US 11,610,541 B1, IDS dated May 8, 2026), although the patent fails to indicate it.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Aug. 21, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2623
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