DETAILED ACTION
This action is responsive to communications: application filed on 11/22/2024.
Applicant’s preliminary amendment filed on 12/05/2024 is being acknowledged and entered: where applicant amended claim 1, added new claims 2-20. Claims 1-20 are pending. Claims 1, 8, and 14 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
3. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification Objections
4a. The Title is objected to because the title of the invention is not descriptive. A
new title is required that is clearly indicative of the invention to which the claims are
directed. The following title is suggested:
"Nand flash programming and method of applying all-string pulse before end of
program operation"
4b. The disclosure "Background" section does not discuss any meaningful problem to be solved or background information and is objected to. 37 C.F.R. 1.71 (b) requires, "The specification must set forth the precise invention for which a patent is solicited, in such manner as to distinguish it from other inventions and from what is old." Applicant is reminded that helpful guidance, as to preparing an application disclosure, is provided in the MPEP under section 608. Notably, MPEP 608.01 (c) provides exemplary use of the heading "Background of the Invention".
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHIMURA et al. (US 2019/0088342 A1).
Regarding independent claim 1, SHIMURA teaches a semiconductor storage device (Fig. 2: 2 “NAND flash memory”. See Fig. 1-Fig. 14 for illustrated components and functionality) comprising:
a plurality of memory strings (Fig. 3: NS) each including a plurality of memory cell transistors connected in series (Fig. 3: MT’s), the plurality of memory strings being connected in parallel to one another (Fig. 3 in context of para [0062]-para [0064]);
a plurality of word lines (Fig. 3: WLs connected to MT’s) connected to gates of the plurality of memory cell transistors (para [0065]);
a block (Fig. 3: BLK) including the plurality of memory strings connected to the plurality of word lines in common (para [0062]); and
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a control circuit (Fig. 2: 22, 24 and associated circuitry) configured to control a write operation on at least part of the plurality of memory cell transistors (Fig. 10 program operation),
wherein the semiconductor storage device is configured to receive a control command related to a first voltage application operation (dummy read prior to end of program operation), a write command and an address and perform data writing (“write instruction” and suspend command associated with dummy read. Fig. 10: S100, Fig. 11: during t0, para [0052]),
the write operation is executed in response to reception of the write command and the address (Fig. 10, Fig. 11 in context of para [0110]),
the control circuit determines, in response to the control command added to the write command and the address, whether to perform the first voltage application operation before the write operation ends (Fig. 10: S102[Wingdings font/0xE0] Yes or No determines whether suspend command is received and whether dummy read for first voltage application is needed),
the first voltage application operation applies a predetermined voltage to the plurality of word lines (Fig. 10 and Fig. 11 in context of para [0122]: “…dummy read operation…voltage VREAD may be applied to all word lines WL of selected block BLK…”), and
when the control command is received, the control circuit executes the first voltage application operation before the write operation ends (Fig. 11: Dummy read operation is performed prior to t7 which is end of program operation).
Regarding claim 2, SHIMURA teaches the semiconductor storage device according to claim 1, wherein when the control command is not received (Fig. 10: S102[Wingdings font/0xE0]No: suspend command not received), the control circuit omits the first voltage application operation executed before the write operation ends (see Fig. 10: S102[Wingdings font/0xE0]No operation method flow).
Regarding claim 3, SHIMURA teaches the semiconductor storage device according to claim 1, further comprising a select gate drain side transistor (Fig. 3: SGD) connected (operably connected) between one of the plurality of memory strings (Fig. 3 NS) and one of bit lines (Fig. 3: BL0), wherein the write operation includes a plurality of loops each including at least a program operation (para [0032], see Fig. 19 loops and last loop), and
when the control command is received,
in a last loop in the write operation (see Fig. 19 loops and last loop),
a fourth voltage is applied to a gate of the select gate drain side transistor (Fig. 11: VSG is applied to SGD transistor gate during t4-t6) and a fifth voltage equal to or higher than the fourth voltage is applied after the fourth voltage is applied (Fig. 11: VSG is applied to SGD transistor gate during t10-t11).
Regarding claim 4, SHIMURA teaches the semiconductor storage device according to claim 1, further comprising a select gate source side transistor (Fig. 3: SGS) connected (operably connected) between one of the plurality of memory strings (Fig. 3: NS) and a source line (Fig. 3: SL), wherein the write operation includes a plurality of loops each including at least a program operation (see Fig. 19 loops and last loop),
when the control command is received, in a last loop in the write operation, a sixth voltage is applied to a gate of the select gate source side transistor (Fig. 11: VSS is applied to SGS transistor gate during t0-t3) and a seventh voltage higher than the sixth voltage is applied after the sixth voltage is applied (Fig. 11: VSG is applied to SGS transistor gate during t9-t11).
Regarding claim 5, SHIMURA teaches the semiconductor storage device according to claim 1, further comprising a source line (Fig. 3: SGS line) connected to the plurality of memory strings (Fig. 3: NS), wherein when the control command is received, in a last loop in the write operation, an eighth voltage is applied to a gate of the source line (Fig. 11: VSG is applied to SGS during t4-t6) and a ninth voltage lower than the eighth voltage is applied after the eighth voltage is applied (Fig. 11: VSS is applied to SGS during t7-t9).
Regarding claim 6, SHIMURA teaches the semiconductor storage device according to claim 1 wherein the first voltage application operation is an all-string read operation providing a voltage to all word lines in the block (para [0122]).
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 8-9 is/are rejected under 35 U.S.C. 103 as being obvious over SHIMURA et al. (US 2019/0088342 A1), in view of Grunzke (US 2018/0254086 A1).
Regarding independent claim 8, SHIMURA teaches a semiconductor storage device (Fig. 2: 2 “nand flash memory”, See Fig. 1-Fig. 25 for illustrated components and functionality) comprising:
a plurality of memory strings (Fig. 3: NS’s) each including a plurality of memory cell transistors connected in series (see Fig. 3), the plurality of memory strings being connected in parallel to one another (See Fig. 3);
a plurality of word lines (Fig. 3: WL0-WL7) connected to gates of the plurality of memory cell transistors (See Fig. 3);
a block including the plurality of memory strings (Fig. 3: BLK) connected to the plurality of word lines in common (see para [0050], Fig. 3); and
a control circuit (Fig. 1: 3, para [0110]: memory controller),
wherein the plurality of word lines include a first word line and a second word line different from the first word line (Fig. 3: see word lines in SU0 and para [0082]: write operation by page i.e. word line),
the plurality of memory cell transistors include a first memory cell transistor and a second memory cell transistor (e.g. Fig. 3: two pages/ WLs WL1, WL2 connected respectively to cell1 in NS1 and cell 2 in NS2 for example),
the first memory cell transistor being connected to the first word line, the second memory cell transistor being connected to the second word line (e.g. Fig. 3: two pages/ WLs WL1, WL2 connected respectively to cell1 in NS1 and cell 2 in NS2 for example),
the control circuit (Fig. 1: 3, para [0110]: memory controller) controls a first write operation and a second write operation (Fig. 12 in context of Fig. 10),
the first write operation (employing Fig. 10 and with Fig. 12: no suspend portion) being performed on the first memory cell transistor (e.g. write operation associated with WL1 and cell1 NOT subject to “creep-up” issue, see para [0102]-para [0103]),
the second write operation (employing Fig. 10 and Fig. 12) being performed on the second memory cell transistor after the first write operation (e.g. write operation associated with WL2 and cell2 subject to “creep-up” issue, see para [0102]-para [0103]).
SHIMURA is silent with respect to the details of utilizing ready/ busy signal in the page programming scheme.
Grunzke teaches -
in a first predetermined duration (Fig. 4: 460_0) that follows an end of the first write operation (Fig. 4: “first page” program) and in which no command is input (Fig. 4: no command input during 460_0), a ready/busy signal maintains a ready state (Fig. 4: R/B# signal state during 460_0),
in a second predetermined duration (Fig. 4: 460_1) follows an end of the second write operation (Fig. 4: “second page” program) and in which no command is input (Fig. 4: no command input during 460_1), the ready/busy signal becomes the ready state (Fig. 4: R/B# signal state during 460_0) and then becomes a busy state (Fig. 4: subsequent R/B# signal state), and
a duration of the first predetermined duration is the same as a duration of the second predetermined duration (Fig. 4: 460_0 and 460_1 duration is same).
SHIMURA and Grunzke are in the same field of art of nand flash memory programming operation and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Grunzke’s programming method and steps into the apparatus of SHIMURA such that programming method with trim setting capability can be employed to improve programming accuracy (Grunzke para [0023])
Regarding claim 9, SHIMURA and Grunzke teach the semiconductor storage device according to claim 8. Grunzke teaches wherein in the second predetermined duration, the ready/busy signal becomes the ready state again and then becomes a busy state again (see Fig. 4: R/B# signal status is inclusive of the limitation).
12. Claims 14, and 17-19 is/are rejected under 35 U.S.C. 103 as being obvious over SHIMURA et al. (US 2019/0088342 A1), in view of TSUBOUCHI (US 2019/0198126 A1).
Regarding independent claim 14, SHIMURA teaches a semiconductor storage device (Fig. 2: 2 “nand flash memory”, See Fig. 1-Fig. 25 for illustrated components and functionality) comprising:
a plurality of memory strings (Fig. 3: NS’s) each including a plurality of memory cell transistors connected in series (see Fig. 3), the plurality of memory strings being connected in parallel to one another (See Fig. 3);
a plurality of word lines (Fig. 3: WL0-WL7) connected to gates of the plurality of memory cell transistors (See Fig. 3);
a block including the plurality of memory strings (Fig. 3: BLK) connected to the plurality of word lines in common (see para [0050], Fig. 3); and
a control circuit (Fig. 1: 3, para [0110]: memory controller),
wherein the plurality of word lines include a first word line and a second word line different from the first word line (Fig. 3: see word lines in SU0 and para [0082]: write operation by page i.e. word line),
the plurality of memory cell transistors include a first memory cell transistor and a second memory cell transistor (e.g. Fig. 3: two pages/ WLs WL1, WL2 connected respectively to cell1 in NS1 and cell 2 in NS2 for example),
the first memory cell transistor being connected to the first word line, the second memory cell transistor being connected to the second word line (e.g. Fig. 3: two pages/ WLs WL1, WL2 connected respectively to cell1 in NS1 and cell 2 in NS2 for example),
the control circuit (Fig. 1: 3, para [0110]: memory controller) controls a first write operation and a second write operation (Fig. 12 in context of Fig. 10),
the first write operation (employing Fig. 10 and with Fig. 12: no suspend portion) being performed on the first memory cell transistor (e.g. write operation associated with WL1 and cell1 NOT subject to “creep-up” issue, see para [0102]-para [0103]),
the second write operation (employing Fig. 10 and Fig. 12) being performed on the second memory cell transistor after the first write operation (e.g. write operation associated with WL2 and cell2 subject to “creep-up” issue, see para [0102]-para [0103]),
the first and second write operations include a plurality of loops each including at least a program operation (see e.g. Fig. 12 last program loop with program and verify applicable for second programming, see also Fig. 10 for first programming),
a last loop in the first write operation performs the program operation and does not perform a verify operation and a first voltage application operation (Fig. 10: S103[Wingdings font/0xE0]S104[Wingdings font/0xE0]S105[Wingdings font/0xE0] End) and with Fig. 12: no suspend portion employed) that applies a predetermined voltage to the first- and second- word lines, and
a last loop in the second write operation (employing Fig. 10 and Fig. 12 in a second page operation) performs the program operation and the first voltage application operation (para [0134]: “…all word lines WL of selected block BLK are directly applied with creep-up voltage VCREEPUP during the suspend period…. See Fig. 22: VCREEPUP and see also para [0082]), and does not perform a verify operation.
SHIMURA is silent with respect to skipping a program-verify step in the last loop of program operation.
TSUBOUCHI teaches skipping a program-verify step in the last loop of program operation (Fig. 9 in context of para [0118]-para [0119]).
SHIMURA and TSUBOUCHI are in the same field of endeavor of nand flash memory programming operation and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine TSUBOUCHI’s program steps into the apparatus of SHIMURA such that programming method can be employed to “prevent threshold fluctuation: and improve STDR (TSUBOUCHI para [0109]).
Regarding claim 17, SHIMURA and TSUBOUCHI teach the semiconductor storage device according to claim 14, further comprising a select gate drain side transistor connected between one of the plurality of memory strings and one of bit lines, wherein in the last loop in the second write operation, a fourth voltage is applied to a gate of the select gate drain side transistor and a fifth voltage equal to or higher than the fourth voltage is applied after the fourth voltage is applied. (See claim 3 rejection analysis)
Regarding claim 18, SHIMURA and TSUBOUCHI teach the semiconductor storage device according to claim 14, further comprising a select gate source side transistor connected between one of the plurality of memory strings and a source line, wherein in the last loop in the second write operation, a sixth voltage is applied to a gate of the select gate source side transistor and a seventh voltage higher than the sixth voltage is applied after the sixth voltage is applied. (See claim 4 rejection analysis)
Regarding claim 19, SHIMURA and TSUBOUCHI teach the semiconductor storage device according to claim 14, further comprising a source line connected to the plurality of memory strings, wherein in the last loop in the second write operation, an eighth voltage is applied to a gate of the source line and a ninth voltage lower than the eighth voltage is applied after the eighth voltage is applied. (See claim 5 rejection analysis)
Double Patenting
13. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
14. Claims 1 and 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. US 12,183,389 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because.
Regarding independent claim 1, US 12,183,389 B2 teaches a semiconductor storage device (US 12,183,389 B2: claims 1-10, and 15-17) comprising:
a plurality of memory strings each including a plurality of memory cell transistors connected in series, the plurality of memory strings being connected in parallel to one another; (US 12,183,389 B2: claim 1, lines 2-5)
a plurality of word lines connected to gates of the plurality of memory cell transistors; (US 12,183,389 B2: claim 1, lines 6-7)
a block including the plurality of memory strings connected to the plurality of word lines in common; and (US 12,183,389 B2: claim 1, lines 8-9)
a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors, (US 12,183,389 B2: claim 1, lines 10-12)
wherein the semiconductor storage device is configured to receive a control command related to a first voltage application operation, a write command and an address and perform data writing, (US 12,183,389 B2: claim 15, lines 13-16: “control command” used. See also claim 1, lines 13-15)
the write operation is executed in response to reception of the write command and the address, (US 12,183,389 B2: claim 15, lines 16-21; claim 1, lines 13-21)
the control circuit determines, in response to the control command added to the write command and the address whether to perform the first voltage application operation before the write operation ends, (US 12,183,389 B2: claim 15, lines 16-21; claim 1, lines 13-21)
the first voltage application operation applies a predetermined voltage to the plurality of word lines, and when the control command is received, the control circuit executes the first voltage application operation before the write operation ends. (US 12,183,389 B2: claim 1, lines 22-27; claim 15, lines 12-26)
Regarding independent claim 14, US 12,183,389 B2 teaches a semiconductor storage device (US 12,183,389 B2: claims 11-17) comprising:
a plurality of memory strings each including a plurality of memory cell transistors connected in series, the plurality of memory strings being connected in parallel to one another (US 12,183,389 B2: claim 11, lines 1-9); a plurality of word lines connected to gates of the plurality of memory cell transistors (US 12,183,389 B2: claim 11, lines 1-9); a block including the plurality of memory strings connected to the plurality of word lines in common; and (US 12,183,389 B2: claim 11, lines 1-9)
a control circuit, wherein the plurality of word lines include a first word line and a second word line different from the first word line, (US 12,183,389 B2: claim 11, lines 10-12)
the plurality of memory cell transistors include a first memory cell transistor and a second memory cell transistor, the first memory cell transistor being connected to the first word line, the second memory cell transistor being connected to the second word line, (US 12,183,389 B2: claim 11, lines 13-17)
the control circuit controls a first write operation and a second write operation, the first write operation being performed on the first memory cell transistor, the second write operation being performed on the second memory cell transistor after the first write operation, (US 12,183,389 B2: claim 11, lines 18-22)
the first and second write operations include a plurality of loops each including at least a program operation, (US 12,183,389 B2: claim 11, lines 23-24)
a last loop in the first write operation performs the program operation and does not perform a first voltage application operation that applies a predetermined voltage to the first- and second- word lines, and (US 12,183,389 B2: claim 11, lines 25-29)
a last loop in the second write operation performs the program operation and the first voltage application operation. (US 12,183,389 B2: claim 11, lines 30-33)
Allowable Subject Matter
Claims 7, 10-13, 15-16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Further, any associated double patenting rejection must be over-come.
Regarding claims above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
SHIBATA (US 2020/0211655 A1): Fig. 1-Fig. 190 applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached at (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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