Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 21-40 are presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 21-22, 24-25, 27-29, 31-32, 34-38 and 40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1- 20 of U.S. Patent No. 12190990. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-22, 24-25 and 27-29 of the examined application are anticipated and the same scope of invention by claims 1-10 of the reference such as a method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and
It is noted that outputting a first/second command/address value to a dynamic random access memory in the examined application has the same scope as receiving a first/second command/address value by a dynamic random access memory in the reference application.
The limitation “charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command” in a claim 21 of the examined application is obvious to a claim 1 of the reference 9570126 below.
Claims 23 and 33 recite a limitation “sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal” including a claims 24 and 34 is obvious to a claim 3 of the reference 11270741 below.
Claim 26 recites a limitation “to clear the first sub-row of data from the first set of sense amplifiers concurrently with charging the bit lines to the precharge voltage level” is obvious to a claim 13 of the reference 9570126 below.
Claims 30 and 39 recite a limitation a “bank address bit-field that specifies a first storage bank from among a plurality of storage banks within the DRAM” which is obvious to a claim 10 of the reference 10388337 below.
Claims 31-32, 34-38 of the examined application are anticipated and the same scope of invention by claims 10-19 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claim 40 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory control component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and
5. Claims 21-40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11804250. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-30 of the examined application are anticipated and the same scope of invention by claims 1-10 of the reference such as a method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers;
It is noted that outputting a first/second command/address value to a dynamic random access memory in the examined application has the same scope as receiving a first/second command/address value by a dynamic random access memory in the reference application.
The limitation “charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command” in a claim 21 of the examined application is obvious to a claim 1 of the reference 9570126 below.
Claims 23 and 33 recite a limitation “sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal” including a claims 24 and 34 is obvious to a claim 3 of the reference 11270741 below.
Claim 26 recites a limitation “to clear the first sub-row of data from the first set of sense amplifiers concurrently with charging the bit lines to the precharge voltage level” is obvious to a claim 13 of the reference 9570126 below.
Claims 30 and 39 recite a limitation a “bank address bit-field that specifies a first storage bank from among a plurality of storage banks within the DRAM” which is obvious to a claim 10 of the reference 10388337 below.
Claims 31-39 of the examined application are anticipated and the same scope of invention by claims 10-19 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claim 39 of the examined application is obvious to claim 10 of the reference.
Claim 40 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory control component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
6. Claims 21-40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-18 and 20 of U.S. Patent No. 11270741. Although the conflicting claims are not identical, they are not patent9ably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-30 of the examined application are anticipated and the same scope of invention by claims 1-10 of the reference such as a method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and
The limitation “charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command” in claim 21 of the examined application is obvious to claim 1 of the reference 9570126 below.
Claim 26 recites a limitation “to clear the first sub-row of data from the first set of sense amplifiers concurrently with charging the bit lines to the precharge voltage level” is obvious to a claim 13 of the reference 9570126 below.
The examined application claims 25-26 are also inherent/obvious over the reference claims because the claim seems to differ from the reference in that the claimed invention of the examined application recites a data signal interface while in the reference claim is silent, however, it is inherent in a memory system in order to communication between a host or a memory controller and a memory device, for example, Fig. 14 of reference discloses the command/address signaling interface).
Claims 31-39 of the examined application are anticipated and the same scope of invention by claims 10-18 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.02
Claim 40 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory control component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
7. Claims 21-40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-18 and 20 of U.S. Patent No. 10811062. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-30 of the examined application are anticipated and the same scope of invention by claims 1-10 of the reference such as a method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and
The limitation “charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command” in a claim 21 of the examined application is obvious to a claim 1 of the reference 9570126 below.
Claim 23 recites a limitation “sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal” including a claim 24 is obvious to a claim 3 of the reference 11270741 above.
Claim 26 recites a limitation “to clear the first sub-row of data from the first set of sense amplifiers concurrently with charging the bit lines to the precharge voltage level” is obvious to a claim 13 of the reference 9570126 below.
The examined application claims 25-26 are also inherent/obvious over the reference claims because the claim seems to differ from the reference in that the claimed invention of the examined application recites a data signal interface while in the reference claim is silent, however, it is inherent in a memory system in order to communication between a host or a memory controller and a memory device, for example, Fig. 14 of reference discloses the command/address signaling interface).
The examined application claims 29 and 38 are also inherent/obvious over the reference claims, because the claim seems to differ from the reference in that the claimed invention of the examined application recites … a third command/address value while in the reference claim is silent, however, there are multiple of command/address values for accessing in memory component. Therefore, one of ordinary skill in the art would have recognized that the third address would be used to write or read as shown in Figs. 4A and 8 of the reference.
Claims 31-39 of the examined application are anticipated and the same scope of invention by claims 11-18 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claim 40 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory control component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
8. Claims 21-40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-7, 10-18 and 21 of U.S. Patent No. 10388337. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-30 of the examined application are anticipated and the same scope of invention by claims 1-7 of the reference such as a method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers;
The limitation “charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command” in a claim 21 of the examined application is obvious to a claim 1 of the reference 9570126 below.
Claim 23 recites a limitation “sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal” including a claim 24 is obvious to a claim 3 of the reference 11270741 above.
Claim 26 recites a limitation “to clear the first sub-row of data from the first set of sense amplifiers concurrently with charging the bit lines to the precharge voltage level” is obvious to a claim 13 of the reference 9570126 below.
The examined application claims 25-26 are also inherent/obvious over the reference claims because the claim seems to differ from the reference in that the claimed invention of the examined application recites a data signal interface, while the reference claim is silent, however, it is inherent in a memory system in order to communication between a host or a memory controller and a memory device, for example, Fig. 14 of reference discloses the command/address signaling interface.
The examined application claims 29 and 38 are also inherent/obvious over the reference claims, because the claim seems to differ from the reference in that the claimed invention of the examined application recites … a third command/address value while in the reference claim is silent, however, there are multiple of command/address values for accessing in memory component. Therefore, one of ordinary skill in the art would have recognized that the third address would be used to write or read as shown in Figs. 4A and 8 of the reference.
Claims 31-39 of the examined application are anticipated and the same scope of invention by claims 10-18 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claim 40 of the examined application are anticipated and the same scope of invention by claim 21 of the reference such as a memory control component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
9. Claims 21-40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-8, 11-17 and 20 of U.S. Patent No. (USP) 9911468. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-30 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers;
The limitation “charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command” in a claim 21 of the examined application is obvious to a claim 1 of the reference 9570126 below.
Claims 23 and 33 recite a limitation “sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal” including a claims 24 and 34 is obvious to a claim 3 of the reference 11270741 above.
Claim 26 recites a limitation “to clear the first sub-row of data from the first set of sense amplifiers concurrently with charging the bit lines to the precharge voltage level” is obvious to a claim 13 of the reference 9570126 below.
Claims 30 and 39 recite a limitation a “bank address bit-field that specifies a first storage bank from among a plurality of storage banks within the DRAM” which is obvious to a claim 10 of the reference 10388337 above.
The examined application claims 25-26 are also inherent/obvious over the reference claims because the claim seems to differ from the reference in that the claimed invention of the examined application recites a data signal interface while in the reference claim is silent, however, it is inherent in a memory system in order to communication between a host or a memory controller and a memory device, for example, Fig. 14 of reference discloses the command/address signaling interface.
The examined application claims 29 and 38 are also inherent/obvious over the reference claims, because the claim seems to differ from the reference in that the claimed invention of the examined application recites … a third command/address value while in the reference claim is silent, however, there are multiple of command/address values for accessing in memory component. Therefore, one of ordinary skill in the art would have recognized that the third address would be used to write or read as shown in Figs. 4A and 8 of the reference.
The examined application claims 30 and 39 are inherent/obvious over the reference claims because the claim seems to differ from the reference in that the claimed invention of the examined application recites executing a precharge operation with respect to the first sub-row of storage cells in response to the column command after accessing a column of data within the first sub-row region of the sense amplifier bank, however, it is inherent in a memory device Therefore, one of ordinary skill in the art would have recognized in the memory the storage array is precharged before or after a reading operation as disclosed by the reference USP 9570126 in claim 12 or the reference USP 10388337 in claim 11.
Claims 31-39 of the examined application are anticipated and the same scope of invention by claims 11-17 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claim 40 of the examined application are anticipated and the same scope of invention by claim 20 of the reference such as a memory control component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
10. Claims 21-40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-4, 6-15 and 17-22 of U.S. Patent No. (USP) 9570126. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-30 of the examined application are anticipated and the same scope of invention by claims 1-4 and 6-11 of the reference such as a method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claims 23 and 33 recite a limitation “sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal” including a claims 24 and 34 is obvious to a claim 3 of the reference 11270741 above.
Claims 30 and 39 recite a limitation a “bank address bit-field that specifies a first storage bank from among a plurality of storage banks within the DRAM” which is obvious to a claim 10 of the reference 10388337 above.
The examined application claims 29 and 38 are also inherent/obvious over the reference claims, because the claim seems to differ from the reference in that the claimed invention of the examined application recites … a third command/address value while in the reference is silent, however, there are multiple of command/address values for accessing in memory component. Therefore, one of ordinary skill in the art would have recognized that the third address would be used to write or read as shown in Figs. 4A and 8 of the reference.
Claims 31-39 of the examined application are anticipated and the same scope of invention by claims 11-17 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claim 40 of the examined application are anticipated and the same scope of invention by claim 22 of the reference such as a memory control component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
11. Claims 21-40 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-4 and 5-16 of U.S. Patent No 9330735. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 21-30 of the examined application are anticipated and the same scope of invention by claims 1-4 and 6-9 of the reference such as method of operation within a memory control component, the method comprising: outputting a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and after outputting the row command and the first address, outputting a first column command and a second address to the DRAM component, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub-row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers;
The limitation “charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command” in a claim 21 of the examined application is obvious to a claim 1 of the reference 9570126 above.
Claims 23 and 33 recite a limitation “sequence of one or more command/address transmit intervals defined by one or more respective transitions of a first clock signal” including a claims 24 and 34 is obvious to a claim 3 of the reference 11270741 above.
Claims 30 and 39 recite a limitation a “bank address bit-field that specifies a first storage bank from among a plurality of storage banks within the DRAM” which is obvious to a claim 10 of the reference 10388337 above.
The examined application claims 29 and 38 are also inherent/obvious over the reference claims, because the claim seems to differ from the reference in that the claimed invention of the examined application recites … a third command/address value while in the reference is silent, however, there are multiple of command/address values for accessing in memory component. Therefore, one of ordinary skill in the art would have recognized that the third address would be used to write or read as shown in Figs. 4A and 8 of the reference.
The examined application claims 30 and 39 are inherent/obvious over the reference claims because the claim seems to differ from the reference in that the claimed invention of the examined application recites executing a precharge operation with respect to the first sub-row of storage cells in response to the column command after accessing a column of data within the first sub-row region of the sense amplifier bank, however, it is inherent in a memory device Therefore, one of ordinary skill in the art would have recognized in the memory the storage array is precharged before or after a reading operation as disclosed by the reference USP 9570126 in claim 12 or the reference USP 10388337 in claim 11.
Claims 31-39 of the examined application are anticipated and the same scope of invention by claims 10-16 of the reference such as a memory control component comprising: a first signaling interface; and control circuitry to output via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
Claim 40 of the examined application are anticipated and the same scope of invention by claims 10 of the reference such as a component comprising: a first signaling interface; and means for outputting via the first signaling interface: a row command and a first address to a dynamic random access memory (DRAM) component, the first address specifying a first row of storage cells within a storage array of the DRAM component; and a first column command and a second address to the DRAM component after outputting the row command and the first address, the second address specifying a first column of data within a first sub-row of storage cells included within the first row of storage cells specified by the first address, the first column command instructing the DRAM component to: transfer a first sub-row of data, including the first column of data, from the first sub- row of storage cells to a first set of sense amplifiers within the DRAM component via bit lines coupled between the first sub-row of storage cells and the first set of sense amplifiers; and charge the bit lines to a precharge voltage level a first predetermined time after receiving the first column command.
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14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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