DETAILED ACTION
This Office Action is in response to applicant’s communication filed on 11.22.24. In view of this communication, claims 1-13 are now pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims below are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitations “the at least one substrate is integrated in a coating on a busbar”. Claim 8 depends upon claim 1 and claim 1 recites “at least one substrate placed on or above a coating on at least one of the semiconductor packages” If the coating is the same, then there seems to be a conflict between “above” in claim 1 and “integrated” in claim 8. If the coating is different, then it needs to be recited accordingly in claim 8. To advance prosecution, Examiner will ignore “above” and interpret as “the coating”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-7, 9, 11-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Weis et al (US20240007015A1 Filing Date 6.27.23), hereinafter Weis.
Regarding Claim 1, Weis discloses (Figs 3-4, 10-11) an inverter[Abstract] comprising:
a base plate(2) ;
at least one half bridge [Para 0026 discloses “Semiconductor packages 4 are generally arranged in mutual opposition such that, in each case, two of the latter form a half-bridge, wherein one semiconductor package 4 functions as a high-side switch 41 and the other functions as a low-side switch 40, each of which comprises two mutually parallel-connected power semiconductors”] on the base plate, which has a high side for at least one semiconductor package forming a high side switch (41), and a low side for at least one parallel semiconductor package forming a low side switch (40), wherein each semiconductor package is encased in a non-conductive coating [0027 discloses “The term semiconductor package 4 describes a sheathed power semiconductor (chip), inclusive of (unsheathed) terminal lugs for electrical or signal contact-connection”]; and
a temperature measuring system (Figs 10-11) configured to measure a temperature of the semiconductor packages in the inverter, wherein the inverter includes at least one phase (P1), wherein the temperature measuring system comprises:
at least one substrate (10) placed on or above a coating on at least one of the semiconductor packages (Fig 11); and
at least one temperature measuring element (106) on or in the at least one substrate (10), which is configured to at least detect a surface temperature of the coating on at least one semiconductor package [0036 discloses “temperature sensors 106 to be led through to the underside of the DC-negative conductor rail 6, in order to measure the temperature of semiconductor packages 4”].
PNG
media_image1.png
486
542
media_image1.png
Greyscale
Regarding Claim 2, Weis discloses the inverter according to claim 1. Weis further discloses wherein the temperature measuring element (106) comprises a temperature sensor [0036] or resistor strip.
Regarding Claim 3, Weis discloses the inverter according to claim 1. Weis further discloses
wherein the temperature measuring system comprises: a temperature measuring element (106) for each semiconductor package, or for each phase, or for each high side and/or low side [0067 discloses “one or more temperature sensors 106 can also be connected to the signal bus board for the direct inspection of the semiconductor packages 4, more specifically, and independently, the high-side 40 and low-side 41 thereof respectively, i.e. for monitoring the temperature thereof”], or for all of the phases.
Regarding Claim 6, Weis discloses the inverter according to claim 1. Weis further discloses
wherein the at least one substrate (10) extends over (Fig 11) the semiconductor packages (4).
Regarding Claim 7, Weis discloses the inverter according to claim 1. Weis further discloses
wherein the at least one substrate (10) is attached to the semiconductor packages (4)[0062 discloses a screw attachment between 10 and 2].
Regarding Claim 9, Weis discloses the inverter according to claim 1 . Weis further discloses wherein the at least one substrate (10) is a film, a flexible film, a PCB [0062 discloses "[Para 0062 discloses “The signal busboard 10 is a circuit board in or upon which signal lines are routed and components are arranged”], or a copper strip.
Regarding Claim 11, Weis discloses the inverter according to claim 1. Weis further discloses
an electronics module [0003] comprising: the inverter [0003] according to claim 1.
Regarding Claim 12, Weis discloses the inverter according to claim 1. Weis further discloses
an electric motor [0003] for a vehicle [0003] comprising: at least one electric drive [0003]; and the electronics module according to claim 11 configured to control the electric motor.
Regarding Claim 13, Weis further discloses a vehicle [0003] comprising: the electric motor [0003] according to claim 12.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Weis in view of Feurtado et al (US20200053900A1), hereinafter Feurtado.
Regarding Claim 4, Weis discloses the inverter according to claim 1 . Weis further discloses wherein the at least one substrate (10) extends in a shape over one or all of the at least one phase (P1)(10 has a shape that extends over each phase) but does not explicitly disclose a U-shape.
Feurtado discloses (Fig 18) substrate (616) with a U-shape (Fig 18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed inverter of Weis with U shaped substrate as taught by Feurtado in order to have a shape that is minimally required to support the various electronic components as well as make required electrical connections.
PNG
media_image2.png
656
530
media_image2.png
Greyscale
Regarding Claim 5, Weis discloses the inverter according to claim 1 . Weis does not explicitly disclose wherein the at least one substrate is formed by two strips, each of which extends continuously over one or all of the at least one phase, over the high side or low side.
Feurtado discloses (Fig 10) wherein the at least one substrate (616) is formed by two strips (616,616), each of which extends continuously over one or all of the at least one phase (Fig 12B), over (this is a relative term) the high side or low side (Examiner interprets high or low side as V+ or V- and Fig 12B is a half bridge structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed inverter of Weis with substrate in two strips as taught by Feurtado in order to have a shape that is minimally required to support the various electronic components as well as make required electrical connections.
PNG
media_image3.png
776
504
media_image3.png
Greyscale
PNG
media_image4.png
534
372
media_image4.png
Greyscale
Claims 8,10 are rejected under 35 U.S.C. 103 as being unpatentable over Weis in view of Speinle et al (US20240291414A1 PCT Filed 8.2.22), hereinafter Speinle.
Regarding Claim 10, Weis discloses the inverter according to claim 1 . Weis does not explicitly disclose wherein the at least one substrate is integrated in a coating on a busbar directly above the semiconductor packages.
Speinle discloses (Fig 2) wherein the at least one substrate (10) is integrated in a coating (10 is a flexible circuit which is integrated with busbar 11 and temperature sensor 6) on a busbar (11) directly above (above is a relative term) the semiconductor packages (S1,S2,S3,S4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed inverter of Weis with integrated substrate with busbar as taught by Speinle in order to have a simplified circuit that contains sensors and power lines.
PNG
media_image5.png
466
756
media_image5.png
Greyscale
Regarding Claim 10, Weis discloses the inverter according to claim 1 . Weis does not explicitly disclose wherein each of the at least one substrate contains at least one contact point with which the temperature measuring system is connected to an external processor ( Weis is Para 0067 does disclose “Signals can then be read out from the signal busboard 10, whereafter e.g. the controller of the semiconductor packages 4 can then be adjusted” but does not disclose “contact point” similar to instant claim and invention.
Speinle discloses (Figs 1-2) wherein each of the at least one substrate (10) contains at least one contact point (12 contact point) with which the temperature measuring system (6) is connected to an external processor (3)[Para 0024].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed inverter of Weis with temperature measuring system connection point with external processor as taught by Speinle in order to have a way to transfer sensor signal to a processor and controller so that temperature is monitored and not allowed to exceed predetermined limits to avoid failure.
PNG
media_image6.png
460
760
media_image6.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VISWANATHAN SUBRAMANIAN whose telephone number is (571)272-4814. The examiner can normally be reached Monday - Friday 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christopher M Koehler can be reached at 5712723560. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VISWANATHAN SUBRAMANIAN/Examiner, Art Unit 2834
Prosecution Insights