DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-11, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over SONG (US Pub.: 2010/0235700) in view of Malisic et al. (US Pub.: 2024/0095138).
As per claim 1, SONG teaches/suggests an apparatus comprising: one or more components configured to: having a set of instructions based on a type of test being performed for memory device (e.g. associated with read/write commands, address signal: Fig. 1; [0030]); inject the set of instructions into a data path of memory device (e.g. associated with transmitting read/write commands, address signal: Fig. 1; [0030]; [0037]); extract a set of data from the data path, wherein the set of data is generated by the data path based on the set of instructions; and determine a test result based on the set of data (e.g. associated with comparing data outputted from the DUT with corresponding data from latch unit to determine if DUT is normal or defective: Fig. 1; [0050]) (Fig. 1-3; and [0008]-[0014]; and [0029]-[0050]).
SONG does not teach the apparatus comprising:
generate instruction for the CXL compliant device; and
communicating with the CXL compliant device.
Malisic teaches/suggests an apparatus comprising: generate instruction for the CXL compliant device (e.g. associated with testing workloads such as instructions are generated for CXL DUT/memory: [0035]; [0039]); and communicating with the CXL compliant device (e.g. associated with communicating with CXL DUT/memory for testing: [0083]-[0085]) ([0015]; [0033]-[0040]; [0083]-[0085]) (Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; and [0077]-[0085]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Malisic’s testing architecture into SONG’s apparatus for the benefit of efficiently and effectively test resources in terms of performance and cost (Malisic, [0082]) to obtain the invention as specified in claim 1.
As per claim 2, SONG and Malisic teach/suggest all the claimed features of claim 1 above, where SONG and Malisic further teach/suggest the apparatus comprising: wherein the one or more components, to determine the test result, are configured to compare the set of data to an expected set of data (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]).
As per claim 3, SONG and Malisic teach/suggest all the claimed features of claim 2 above, where SONG and Malisic further teach/suggest the apparatus comprising: wherein the one or more components, to compare the set of data to the expected set of data, are configured to perform a bitwise exclusive or (XOR) operation using bit values of the set of data and bit values of the expected set of data (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]).
As per claim 6, SONG and Malisic teach/suggest all the claimed features of claim 1 above, where SONG and Malisic further teach/suggest the apparatus comprising: wherein the set of instructions is associated with at least one of a read command or a write command (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]).
As per claim 7, SONG and Malisic teach/suggest all the claimed features of claim 1 above, where SONG and Malisic further teach/suggest the apparatus comprising: wherein the set of instructions is associated with at least one of fixed data or pseudo-randomly generated data (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 8, SONG and Malisic teach/suggest all the claimed features of claim 1 above, where SONG and Malisic further teach/suggest the apparatus comprising: wherein the set of instructions is associated with at least one of a set of sequential memory addresses or a set of pseudo-random generated memory addresses (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 9, SONG teaches/suggests a method comprising: having a set of instructions based on a type of test being performed for memory device (e.g. associated with read/write commands, address signal: Fig. 1; [0030]); injecting the set of instructions into a data path of memory device (e.g. associated with transmitting read/write commands, address signal: Fig. 1; [0030]; [0037]); and extracting, by a comparator component of the memory device, a set of data from the data path, wherein the set of data is generated by the data path based on the set of instructions; and determining a test result based on the set of data (e.g. associated with comparing data outputted from the DUT with corresponding data from latch unit to determine if DUT is normal or defective: Fig. 1; [0050]) (Fig. 1-3; and [0008]-[0014]; [0029]-[0050]).
SONG does not teach the method comprising:
transmitting, by a control unit component of a compute express link (CXL) compliant memory device to a generator component of the CXL compliant memory device, an indication of a type of test being performed for the CXL compliant memory device;
generating, by the generator component, instruction based on the type of test being performed for the CXL compliant device;
communicate, by the generator component, with the CXL compliant device;
operating, by at least one of the control unit component or a component of the CXL compliant device, accordingly; and operating, by the control unit component, accordingly.
Malisic teaches/suggests a method comprising: transmitting, by a control unit component of a compute express link (CXL) compliant memory device to a generator component of the CXL compliant memory device, an indication of a type of test being performed for the CXL compliant memory device (e.g. associated with corresponding signaling for configuring the test system to perform the corresponding test process: [0038]-[0039]); generating, by the generator component, instruction based on the type of test being performed for the CXL compliant device (e.g. associated with testing workloads such as instructions are generated for CXL DUT/memory: [0035]; [0039]); communicate, by the generator component, with the CXL compliant device (e.g. associated with communicating with CXL DUT/memory for testing: [0083]-[0085]) ([0015]; [0033]-[0040]; [0083]-[0085]); operating, by at least one of the control unit component or a component of the CXL compliant device, accordingly; and operating, by the control unit component, accordingly (Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; and [0077]-[0085]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Malisic’s testing architecture into SONG’s apparatus for the benefit of efficiently and effectively test resources in terms of performance and cost (Malisic, [0082]) to obtain the invention as specified in claim 9.
As per claim 10, SONG and Malisic teach/suggest all the claimed features of claim 9 above, where SONG and Malisic further teach/suggest the method further comprising receiving, by the control unit component from the comparator component, an indication of a comparison of the set of data to an expected set of data, wherein determining the test result is based on the comparison of the set of data to the expected set of data (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]).
As per claim 11, SONG and Malisic teach/suggest all the claimed features of claim 10 above, where SONG and Malisic further teach/suggest the method further comprising performing, by the comparator component, a bitwise exclusive or (XOR) operation using bit values of the set of data and bit values of the expected set of data, wherein the comparison of the set of data to the expected set of data is based on the bitwise XOR operation (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]).
As per claim 14, SONG and Malisic teach/suggest all the claimed features of claim 9 above, where SONG and Malisic further teach/suggest the method further comprising wherein the set of instructions is associated with at least one of a read command or a write command (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]).
As per claim 15, SONG and Malisic teach/suggest all the claimed features of claim 9 above, where SONG and Malisic further teach/suggest the method further comprising wherein the set of instructions is associated with at least one of fixed data or pseudo-randomly generated data (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 16, SONG and Malisic teach/suggest all the claimed features of claim 9 above, where SONG and Malisic further teach/suggest the method further comprising wherein the set of instructions is associated with at least one of a set of sequential memory addresses or a set of pseudo-random generated memory addresses (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
Claims 4, 12, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over SONG (US Pub.: 2010/0235700) in view of Malisic et al. (US Pub.: 2024/0095138) and Goto et al. (US Pub.: 2002/0085418).
As per claim 4, SONG and Malisic teach/suggest all the claimed features of claim 1 above, where SONG and Malisic further teach/suggest the apparatus comprising: wherein the one or more components, to inject the set of instructions into the data path, are configured to use a first multiplexer associated with an incoming data buffer of the data path, and wherein the one or more components, to extract the set of data from the data path, are configured to use a second multiplexer associated with an outgoing data buffer of the data path (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]), but SONG and Malisic do not teach the apparatus comprising: a first multiplexer associated with an incoming data buffer of path; and a second multiplexer associated with an outgoing data buffer of path.
Goto teaches/suggests a memory device comprising: a first multiplexer (e.g. associate with multiplexer (7) in Fig. 9) associated with an incoming data buffer (e.g. associate with input buffer (17) in Fig. 9) of path; and a second multiplexer (e.g. associate with multiplexer (7) in Fig. 9) associated with an outgoing data buffer (e.g. associate with output buffer (15) in Fig. 9) of path (Fig. 9).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Goto’s memory architecture into SONG and Malisic’s apparatus for the benefit of implementing a robust storage capacity that can be easily changed (Goto, [0007]) to obtain the invention as specified in claim 4.
As per claim 12, claim 12 is rejected in accordance to the same rational and reasoning as the above rejection of claim 4.
As per claim 17, SONG teaches/suggests a memory device comprising: a data path (e.g. associated path for communicating data, read/write commands, address signal: Fig. 1; [0030]; [0037]; [0050]); an apparatus including a comparator component (e.g. associated with component for comparing data outputted from DUT with corresponding data from latch unit: Fig. 1; [0050]); a set of instructions based on the type of test being performed for the memory device (e.g. associated with read/write commands, address signal: Fig. 1; [0030]); inject the set of instructions into the data path (e.g. associated with transmitting read/write commands, address signal: Fig. 1; [0030]; [0037]); extract, by the comparator component, a set of data from the data path, wherein the set of data is generated by the data path based on the set of instructions; and determine a test result for the type of test being performed for the memory device based on the set of data (e.g. associated with comparing data outputted from the DUT with corresponding data from latch unit to determine if DUT is normal or defective: Fig. 1; [0050]) (Fig. 1-3; and [0008]-[0014]; [0029]-[0050]).
SONG do not teach the memory device comprising:
a compute express link (CXL) compliant host interface;
associated with the CXL compliant host interface including an incoming data buffer and an outgoing data buffer; and
a virtual interface test (VIT) apparatus including a control unit component, a generator component, a first multiplexer between the CXL compliant host interface and the incoming data buffer, and a second multiplexer between the outgoing data buffer and the CXL compliant host interface, wherein the VIT apparatus is configured to:
transmit, by the control unit component to the generator component, an indication of a type of test being performed for the memory device, generate, by the generator component, to operate accordingly;
operating, by the generator component and using the first multiplexer, with the incoming data buffer of path
operating, by one of the control unit component and using the second multiplexer, with the outgoing data buffer of path; and operating, by the control unit component, accordingly.
Malisic teaches/suggests a memory device comprising: a compute express link (CXL) compliant host interface (e.g. associated with host (711) being coupled to interface of CXL DUT/memory device in Fig. 7: Fig. 7; [0035]); associated with the CXL compliant host interface (e.g. associated with host (711) being coupled to interface of CXL DUT/memory device in Fig. 7: Fig. 7; [0035]); and a virtual interface test (VIT) apparatus including a control unit component, a generator component, the CXL compliant host interface, and the CXL compliant host interface, wherein the VIT apparatus is configured to: transmit, by the control unit component to the generator component, an indication of a type of test being performed for the memory device, generate, by the generator component, to operate accordingly (e.g. associated with corresponding signaling for configuring the test system to perform the corresponding test process, and then generating testing workloads such as instructions for CXL DUT/memory: [0038]-[0039]); operating, by the generator component, accordingly; and operating, by one of the control unit component, accordingly; and operating, by the control unit component, accordingly (Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; and [0077]-[0085]).
Goto teaches/suggests a memory device comprising: including an incoming data buffer (e.g. associate with input buffer (17) in Fig. 9) and an outgoing data buffer (e.g. associate with output buffer (15) in Fig. 9); a first multiplexer (e.g. associate with multiplexer (7) in Fig. 9) between interface and the incoming data buffer (e.g. associate with input buffer (17) in Fig. 9), and a second multiplexer (e.g. associate with multiplexer (7) in Fig. 9) between the outgoing data buffer (e.g. associate with output buffer (15) in Fig. 9) and interface; operating, using the first multiplexer (e.g. associate with multiplexer (7) in Fig. 9), with the incoming data buffer (e.g. associate with input buffer (17) in Fig. 9) of path; and operating, using the second multiplexer (e.g. associate with multiplexer (7) in Fig. 9), with the outgoing data buffer (e.g. associate with output buffer (15) in Fig. 9) of path (Fig. 9).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Malisic’s testing architecture and Goto’s memory architecture into SONG’s device for the benefit of efficiently and effectively test resources in terms of performance and cost (Malisic, [0082]), and implementing a robust storage capacity that can be easily changed (Goto, [0007]) to obtain the invention as specified in claim 17.
As per claim 18, SONG, Malisic and Goto teach/suggest all the claimed features of claim 17 above, where SONG, Malisic and Goto further teach/suggest the memory device comprising wherein the VIT apparatus is configured to determine the test result based on comparing, by the comparator component, the set of data to an expected set of data (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]; and Goto, Fig. 9).
As per claim 19, SONG, Malisic and Goto teach/suggest all the claimed features of claim 18 above, where SONG, Malisic and Goto further teach/suggest the memory device comprising wherein the VIT apparatus is configured to compare the set of data to the expected set of data by performing, by the comparator component, a bitwise exclusive or (XOR) operation using bit values of the set of data and bit values of the expected set of data (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]; and Goto, Fig. 9).
As per claim 20, SONG, Malisic and Goto teach/suggest all the claimed features of claim 17 above, where SONG, Malisic and Goto further teach/suggest the memory device comprising wherein the set of instructions is associated with at least one of: a read command, a write command, fixed data, pseudo-randomly generated data, a set of sequential memory addresses, or a set of pseudo-random generated memory addresses (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]; and Goto, Fig. 9), wherein it would have been obvious to one of ordinary skilled in the art to further teach/suggest the above claimed features.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over SONG (US Pub.: 2010/0235700) in view of Malisic et al. (US Pub.: 2024/0095138) as applied to claims 1 and 9 above, and further in view of Erickson et al. (US Pub.: 2023/0177176).
As per claim 5, SONG and Malisic teach/suggest all the claimed features of claim 1 above, where SONG and Malisic further teach/suggest the apparatus comprising: wherein the one or more components are further configured to receive control information of the CXL compliant memory device (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]), but SONG and Malisic do not teach/suggest the apparatus comprising: communicating via a side band interface.
Erickson teaches/suggests an apparatus comprising: communicating via a side band interface (Fig. 5; and [0029]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Erickson’s side-band into SONG and Malisic’s apparatus for the benefit of allowing host to communicate without interfering with CXL-related signal transfers (Erickson, [0029]) to obtain the invention as specified in claim 5.
As per claim 13, SONG and Malisic teach/suggest all the claimed features of claim 9 above, where SONG and Malisic further teach/suggest the method further comprising: wherein the control unit component is associated with an interface of the CXL compliant memory device (SONG, Fig. 1-3; [0008]-[0014]; [0029]-[0050]; and Malisic, Fig. 1A-1B; Fig. 7-8; [0015]; [0033]-[0044]; [0077]-[0085]), but SONG and Malisic do not teach/suggest the method comprising: a side band interface.
Erickson teaches/suggests a method comprising: a side band interface (Fig. 5; and [0029]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Erickson’s side-band into SONG and Malisic’s method for the benefit of allowing host to communicate without interfering with CXL-related signal transfers (Erickson, [0029]) to obtain the invention as specified in claim 13.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 April 04, 2026
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