DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 22 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (USPN 2011/0057864 A1).
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As to claim 22, Chung teaches an output control circuit (see at least FIGS. 2-4B; [0053], [0056]) comprising:
an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least FIG. 3, fourth signal processing unit 414a receiving emission control signal OUT and generating inverted emission control signal OUTB; [0013] “the inverted emission control signal corresponding to an inverse of the emission control signal, and a fourth signal processing unit adapted to output a inverted emission control signal based on the emission control signal and the first output signal.”; [0022], [0060]); and
an outputting determining circuit configured to generate an output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least FIG. 3, third signal processing unit 413a selectively controlling N1a based on inverted clock signal CLKB, emission control signal OUT, and inverted emission control signal OUTB; [0030] “the third signal processing unit selectively controlling the voltage at the first node based on the emission control signal, a inverted clock signal, and an inverted emission control signal”; [0059]; [0066] “with the inverted clock signal /Ck at a low level, the tenth transistor M10a and the eleventh transistor M11a are turned on”; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT.”; [0069] “with the inverted clock signal /Ck at a high level, the tenth transistor M10a and the eleventh transistor M11a are turned off”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note the inverted clock signal CLKB reads on the enable signal because CLKB controls M10a and M11a to selectively enable the conductive paths of third signal processing unit 413a and the voltage/signal at N1a reads on the output control signal because N1a controls the conductive state of the circuitry that generates emission control signal OUT).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 18, 20-21 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over In et al. (US 2022/0238063 A1) in view of Chung (USPN 2011/0057864 A1).
As to claim 1, In teaches a gate emission driver comprising: a gate signal block (see at least FIGS. 2A, 3, 8 and [0082] “the emission driver 300 may supply an emission control signal to the emission control lines ED to ELn”; [0119] “The output signals OUT1 and OUT2 may be output as the emission control signal or the scan signal in the display device (for example, 1000 of FIG. 1)”); and
the gate signal block comprises:
a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal (see at least FIGS. 3 and 8; [0145] “The second input circuit 21 may control a voltage of a first node N1 and a voltage of the second node N2 based on the first carry signal CR1 supplied from the output circuit 12 of the first stage ST1, the first inverted carry signal CRB1”; [0148] “The second output circuit 22 may output the second output signal OUT2, the second carry signal CR2, and the second inverted carry signal CRB2, based on the voltage of the first node N1 and the voltage of the second node N2”; [0215] “The first carry signal CR1 of the high level H may be supplied to the third node N3 through the first node N1 of the second stage ST2. Similarly, the second carry signal CR2 of the high level H may be supplied to the supplied third stage ST3” – note first carry signal CR1 reads on previous carry signal, the voltage/control signal established at N3 reads on gate control signal, and CR2 reads on carry signal); and
a second driver configured to output a gate signal based on the gate control signal (see at least FIGS. 3 and 8, output circuit 22; [0119] “The output signals OUT1 and OUT2 may be output as the emission control signal or the scan signal in the display device”; [0217] “the voltage of the high level H may be immediately supplied to the first nodes NN1 and N1 and the third nodes NN3 and N3. Therefore, the fourth transistors T4 and M4 may be completely turned off”; [0222] “an embodiment of the second stage ST2_1 may include the input circuit 21, the output circuit 22, the control circuit 24, the stabilizing circuit 25, and an initialization circuit 26A”; [0224] “the voltage of the first power VGL may be supplied to the fourth node N4. Therefore, the fifth transistor M5 may be turned on, and thus the second output voltage OUT2 of the high level H may be supplied to the first output terminal 205” – note output circuit 22 reads on second driver, the voltage at N3 reads on gate control signal because N3 controls output transistor M4, and OUT2 reads on gate signal);
In does not directly teach an output control signal block configured to control an outputting of the gate signal block, a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal.
Chung teaches an output control signal block configured to control an outputting of the gate signal block (see at least FIGS. 2-4B, particularly FIG. 3, third signal processing unit 413a and fourth signal processing unit 414a; [0030] “the third signal processing unit selectively controlling the voltage at the first node based on the emission control signal, a inverted clock signal, and an inverted emission control signal”; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note third signal processing unit 413a together with fourth signal processing unit 414a reads on the claimed output control signal block); and
the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least FIG. 3, fourth signal processing unit 414a receiving emission control signal OUT and generating inverted emission control signal OUTB; [0013] “the inverted emission control signal corresponding to an inverse of the emission control signal, and a fourth signal processing unit adapted to output a inverted emission control signal based on the emission control signal and the first output signal.”; [0022], [0060]); and
an outputting determining circuit configured to generate an output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least FIG. 3, third signal processing unit 413a selectively controlling N1a based on inverted clock signal CLKB, emission control signal OUT, and inverted emission control signal OUTB; [0030] “the third signal processing unit selectively controlling the voltage at the first node based on the emission control signal, a inverted clock signal, and an inverted emission control signal”; [0059]; [0066] “with the inverted clock signal /Ck at a low level, the tenth transistor M10a and the eleventh transistor M11a are turned on”; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT.”; [0069] “with the inverted clock signal /Ck at a high level, the tenth transistor M10a and the eleventh transistor M11a are turned off”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note the inverted clock signal CLKB reads on the enable signal because CLKB controls M10a and M11a to selectively enable the conductive paths of third signal processing unit 413a and the voltage/signal at N1a reads on the output control signal because N1a controls the conductive state of the circuitry that generates emission control signal OUT).
Chung further teaches controlling an output driving circuit in response to the output control signal (see at least FIG. 3; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note N1a reads on output control signal because its state controls whether the circuitry supplying OUT is conductive).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Chung’s output-control arrangement to In’s gate/emission driver in order to provide selective control over the outputting of In’s gate/emission-control signal. Chung’s output control arrangement provides a known technique directly applicable to the type of gate/emission control output contemplated by In. When Chung’s output-control arrangement is applied to In’s output circuit 22, In’s output circuit 22 outputs the gate signal OUT2 based on In’s gate control signal at N3 and further in response to the output control signal provided by Chung’s output-control arrangement. Therefore, the combination teaches the second driver configured to output the gate signal based on the gate control signal in response to the output control signal, as claimed.
As to claim 18, In teaches a display apparatus comprising:
a display panel comprising a pixel (see at least fig. 1: display panel 100 and pixel PX);
a gate emission driver configured to output a gate signal and an emission signal to the display panel (see at least fig. 1: timing controller 500, scan driver 200/emission driver 300 and [0076] “the scan driver 200 and the emission driver 300 may be defined by portions of a single gate driver.”); and
a data driver configured to output a data voltage to the display panel (see at least fig. 1: data driver 400),
wherein: the gate emission driver comprises:
a gate signal block (see at least [0082] “the emission driver 300 may supply an emission control signal to the emission control lines ED to ELn”);
the gate signal block is configured to:
generate a carry signal and the gate signal based on a previous carry signal (see at least [0215] “the first output terminal 105 of the first stage ST1 may be connected to the first input terminal 201 of the second stage ST2, ... The first carry signal CR1 of the high level H may be supplied to the third node N3 …. Similarly, the second carry signal CR2 .. may be supplied to the supplied third stage ST3); and
output the gate signal in response to an output control signal (see at least [0222] “the output circuit 22”, [0224] “the second output voltage OUT2 of the high level H may be supplied to the first output terminal 205.”).
In does not directly teach an output control signal block configured to control an outputting of the gate signal block, and the output control signal block comprises: an inverter circuit configured to convert the emission signal to an inverted emission signal; and an outputting determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal.
Chung teaches an output control signal block configured to control an outputting of the gate signal block (see at least FIGS. 2-4B, particularly FIG. 3, third signal processing unit 413a and fourth signal processing unit 414a; [0030] “the third signal processing unit selectively controlling the voltage at the first node based on the emission control signal, a inverted clock signal, and an inverted emission control signal”; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note third signal processing unit 413a together with fourth signal processing unit 414a reads on the claimed output control signal block); and
the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least FIG. 3, fourth signal processing unit 414a receiving emission control signal OUT and generating inverted emission control signal OUTB; [0013] “the inverted emission control signal corresponding to an inverse of the emission control signal, and a fourth signal processing unit adapted to output a inverted emission control signal based on the emission control signal and the first output signal.”; [0022], [0060]); and
an outputting determining circuit configured to generate an output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least FIG. 3, third signal processing unit 413a selectively controlling N1a based on inverted clock signal CLKB, emission control signal OUT, and inverted emission control signal OUTB; [0030] “the third signal processing unit selectively controlling the voltage at the first node based on the emission control signal, a inverted clock signal, and an inverted emission control signal”; [0059]; [0066] “with the inverted clock signal /Ck at a low level, the tenth transistor M10a and the eleventh transistor M11a are turned on”; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT.”; [0069] “with the inverted clock signal /Ck at a high level, the tenth transistor M10a and the eleventh transistor M11a are turned off”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note the inverted clock signal CLKB reads on the enable signal because CLKB controls M10a and M11a to selectively enable the conductive paths of third signal processing unit 413a and the voltage/signal at N1a reads on the output control signal because N1a controls the conductive state of the circuitry that generates emission control signal OUT).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Chung’s output-control arrangement to In’s gate/emission driver in order to provide selective control over the outputting of In’s gate/emission-control signal. Chung’s output control arrangement provides a known technique directly applicable to the type of gate/emission control output contemplated by In.
As to claim 28, In teaches an electronic apparatus comprising:
a display panel comprising a pixel (see at least fig. 1: display panel 100 and pixel PX);
a gate emission driver configured to output a gate signal and an emission signal to the display panel (see at least fig. 1: scan driver 200/emission driver 300 and [0076] “the scan driver 200 and the emission driver 300 may be defined by portions of a single gate driver.”); and
a data driver configured to output a data voltage to the display panel (see at least fig. 1: data driver 400),
a driving controller configured to control the gate emission driver and the data driver based on an input control signal (see at least fig. 1: timing controller 500 and [0080] “The timing controller 500 may receive an input control ... The timing controller 500 may generate a first control signal SCS for controlling a driving timing of the scan driver 200, a second control signal ECS for controlling a driving timing of the emission driver 300, and a third control signal DCS for controlling a driving timing of the data driver 400, based on the input control signal, and may provide the first control signal SCS, the second control signal ECS, and the third control signal DCS to the scan driver 200, the emission driver 300, and the data driver 400, respectively.”); and
a processor configured to output the input control signal (see at least [0080] “The timing controller 500 may receive an input control signal and an input image signal from an image source such as an external graphic device.”);
wherein: the gate emission driver comprises:
a gate signal block (see at least [0082] “the emission driver 300 may supply an emission control signal to the emission control lines ED to ELn”);
the gate signal block is configured to:
generate a carry signal and the gate signal based on a previous carry signal (see at least [0215] “the first output terminal 105 of the first stage ST1 may be connected to the first input terminal 201 of the second stage ST2, ... The first carry signal CR1 of the high level H may be supplied to the third node N3 …. Similarly, the second carry signal CR2 .. may be supplied to the supplied third stage ST3); and
output the gate signal in response to an output control signal (see at least [0222] “the output circuit 22”, [0224] “the second output voltage OUT2 of the high level H may be supplied to the first output terminal 205.”).
In does not directly teach an output control signal block configured to control an outputting of the gate signal block, and the output control signal block comprises: an inverter circuit configured to convert the emission signal to an inverted emission signal; and an outputting determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal.
Chung teaches an output control signal block configured to control an outputting of the gate signal block (see at least FIGS. 2-4B, particularly FIG. 3, third signal processing unit 413a and fourth signal processing unit 414a; [0030] “the third signal processing unit selectively controlling the voltage at the first node based on the emission control signal, a inverted clock signal, and an inverted emission control signal”; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note third signal processing unit 413a together with fourth signal processing unit 414a reads on the claimed output control signal block); and
the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least FIG. 3, fourth signal processing unit 414a receiving emission control signal OUT and generating inverted emission control signal OUTB; [0013] “the inverted emission control signal corresponding to an inverse of the emission control signal, and a fourth signal processing unit adapted to output a inverted emission control signal based on the emission control signal and the first output signal.”; [0022], [0060]); and
an outputting determining circuit configured to generate an output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least FIG. 3, third signal processing unit 413a selectively controlling N1a based on inverted clock signal CLKB, emission control signal OUT, and inverted emission control signal OUTB; [0030] “the third signal processing unit selectively controlling the voltage at the first node based on the emission control signal, a inverted clock signal, and an inverted emission control signal”; [0059]; [0066] “with the inverted clock signal /Ck at a low level, the tenth transistor M10a and the eleventh transistor M11a are turned on”; [0068] “When the first node N1a is at a low level, the fifth transistor M5a and seventh transistor M7a are turned on so that a voltage of the first power source VDD is transmitted to the second node N2a and the output terminal OUT.”; [0069] “with the inverted clock signal /Ck at a high level, the tenth transistor M10a and the eleventh transistor M11a are turned off”; [0075] “With the first node N1a at a high level, the fifth transistor M5a and the seventh transistor M7a are turned off. Therefore, a voltage of the first power source VDD is not transmitted to the second node N2a and the output terminal OUT.” – note the inverted clock signal CLKB reads on the enable signal because CLKB controls M10a and M11a to selectively enable the conductive paths of third signal processing unit 413a and the voltage/signal at N1a reads on the output control signal because N1a controls the conductive state of the circuitry that generates emission control signal OUT).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to apply Chung’s output-control arrangement to In’s gate/emission driver in order to provide selective control over the outputting of In’s gate/emission-control signal. Chung’s output control arrangement provides a known technique directly applicable to the type of gate/emission control output contemplated by In.
As to claim 20, the combination of In and Chung teach the display apparatus of claim 18 (see above rejection), wherein: the gate emission driver further comprises an emission signal block, the gate signal block comprises a first gate signal block and a second gate signal block, the output control signal block comprises a first output control signal block and a second output control signal block, the emission signal block, the first gate signal block, and the first output control signal block are located on a first side, and the second gate signal block and the second output control signal block are located on a first side and a second side different from the first side (see In at least fig. 1: scan driver 200/emission driver 300).
As to claim 21, the combination of In and Chung teach the display apparatus of claim 20 (see above rejection), wherein the emission signal block is connected to the second output control signal block through an emission line (see In at least fig. 1: emission driver 300).
Claims 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over In et al. (US 2022/0238063 A1) in view of Chung (USPN 2011/0057864 A1), further in view of Goessel et al. (USPN 2010/0070811 A1).
As to claim 5, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection).
In and Chung do not directly teach wherein when the enable signal has a high level and the emission signal has a low level, the gate signal has an activation level.
Goessel teaches wherein when the enable signal has a high level and the emission signal has a low level, the gate signal has an activation level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note when the enable signal is high, the inverted enable signal is low, and when the emission signal is low, both C-element inputs are low, thereby providing the low output control level used to activate the gate signal).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit of the combination of In and Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
As to claim 6, the combination of In, Chung and Goessel teach the gate emission driver of claim 5 (see above rejection), wherein when the enable signal has the high level and the emission signal has the low level, the output control signal has a low level (see Goessel at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note when both C-element inputs are low, the output is low).
As to claim 7, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection).
In and Chung do not directly teach wherein when the enable signal has a low level and the emission signal has a high level, the gate signal has an inactivation level.
Goessel teaches wherein when the enable signal has a low level and the emission signal has a high level, the gate signal has an inactivation level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note when the enable signal is high, the inverted enable signal is low, and when the emission signal is low, both C-element inputs are low, thereby providing the low output control level used to activate the gate signal. Therefore, the output control signal assumes the high level used to inactivate the gate signal).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit of the combination of In and Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
As to claim 8, the combination of In, Chung and Goessel teach the gate emission driver of claim 7 (see above rejection), wherein when the enable signal has the low level and the emission signal has the high level, the output control signal has a high level (see Goessel at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] – Note the low enable signal produces a high inverted enable signal and, together with the high emission signal, provides two high inputs to C-element).
As to claim 9, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection).
In and Chung do not directly teach wherein when the enable signal has a high level and the emission signal has a high level, the output control signal maintains a previous level.
Goessel teaches wherein when the enable signal has a high level and the emission signal has a high level, the output control signal maintains a previous level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note the high enable signal provides a low inverted enable signal while the emission signal is high, such that the two inputs to the C-element differ.. Therefore, the output control signal maintains its previous level).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit of the combination of In and Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
As to claim 10, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection).
In and Chung do not directly teach wherein when the enable signal has a low level and the emission signal has a low level, the output control signal maintains a previous level.
Goessel teaches wherein when the enable signal has a low level and the emission signal has a low level, the output control signal maintains a previous level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note the low enable signal provides a high inverted enable signal while the emission signal is low, such that the two C-element inputs differ.. Therefore, the output control signal maintains its previous level).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit of the combination of In and Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
Claims 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chung (USPN 2011/0057864 A1) in view of Goessel et al. (USPN 2010/0070811 A1).
As to claim 24, Chung teaches the output control circuit of claim 22 (see above rejection).
Chung does not directly teach wherein when the enable signal has a high level and the emission signal has a low level, the output control signal has a low level.
Goessel teaches wherein when the enable signal has a high level and the emission signal has a low level, the output control signal has a low level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note when both C-element inputs are low, the output is low).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
As to claim 25, Chung teaches the output control circuit of claim 22 (see above rejection).
Chung does not directly teach wherein when the enable signal has a low level and the emission signal has a high level, the output control signal has a high level.
Goessel teaches wherein when the enable signal has a low level and the emission signal has a high level, the output control signal has a high level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] – Note the low enable signal produces a high inverted enable signal and, together with the high emission signal, provides two high inputs to C-element).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit of Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
As to claim 26, Chung teaches the output control circuit of claim 22 (see above rejection).
Chung does not directly teach wherein when the enable signal has a high level and the emission signal has a high level, the output control signal maintains a previous level.
Goessel teaches wherein when the enable signal has a high level and the emission signal has a high level, the output control signal maintains a previous level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note the high enable signal provides a low inverted enable signal while the emission signal is high, such that the two inputs to the C-element differ.. Therefore, the output control signal maintains its previous level).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit of Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
As to claim 27, Chung teaches the output control circuit of claim 22 (see above rejection).
Chung does not directly teach wherein when the enable signal has a low level and the emission signal has a low level, the output control signal maintains a previous level.
Goessel teaches wherein when the enable signal has a low level and the emission signal has a low level, the output control signal maintains a previous level (see at least Figs. 3–4; [0074] “The corrector K 14 .. a parallel connection of k C-elements … each having two inputs and one output”; [0076] “If the values yi=yi′=0 are then applied to the inputs of the C-element … the output denoted y(korr)i carries the value 0 (low) … when yi=yi′=1 is input, the value y(korr)i=1 is output”; [0077] “where yi=1 and yi′=0 … it retains its previous value, so that the previous value of y(korr)i is also output at the output of the C-element. A similar behaviour occurs when yi=0 and yi′=1”; [0078]–[0079] - Note the low enable signal provides a high inverted enable signal while the emission signal is low, such that the two C-element inputs differ.. Therefore, the output control signal maintains its previous level).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to configure the output determining circuit of Chung using the known state retaining C-element logic taught by Goessel, with the inverted enable signal and the emission signal as inputs, in order to provide a stable output control signal that is set to a defined level when the input signals agree and maintains its previous level when the input signals differ. Such a configuration would provide stable control of the outputting of the gate signal during differing control conditions while allowing the output control signal to be set when the control conditions agree.
Allowable Subject Matter
Claims 2-4, 11-17, 19 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art of record teach:
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the output determining circuit comprises: a first determining transistor comprising a control electrode configured to receive the emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first control node; a second determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the first control node, and a second electrode connected to a second control node; a third determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the second control node, and a second electrode connected to a third control node; and a fourth determining transistor comprising a control electrode configured to receive the inverted emission signal, a first electrode connected to the third control node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and the first determining transistor and the second determining transistor are each a P-type transistor and the third determining transistor and the fourth determining transistor are each an N-type transistor.”;
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the gate signal comprises an initialization gate signal, the second driver comprises: a first initialization output transistor comprising a control electrode configured to receive the output control signal, a first electrode connected to a second initialization control node, and a second electrode connected to a third initialization node; a second initialization output transistor comprising a control electrode connected to the third initialization node, a first electrode configured to receive a first power voltage, and a second electrode connected to a fourth initialization node; and a third initialization output transistor comprising a control electrode connected to a first initialization control node, a first electrode connected to the fourth initialization node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and a signal of the fourth initialization node is the initialization gate signal.”;
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the gate signal comprises a compensation gate signal, the second driver comprises: a first compensation output transistor comprising a control electrode configured to receive the output control signal, a first electrode connected to a second compensation control node, and a second electrode connected to a third compensation node; a second compensation output transistor comprising a control electrode connected to the third compensation node, a first electrode configured to receive a first power voltage, and a second electrode connected to a fourth compensation node; and a third compensation output transistor comprising a control electrode connected to a first compensation control node, a first electrode connected to the fourth compensation node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and a signal of the fourth compensation node is the compensation gate signal.”;
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the gate signal comprises a write gate signal, and the gate control signal comprises a first write gate control signal and a second write gate control signal, the second driver comprises: a first write output transistor comprising a control electrode configured to receive the output control signal, a first electrode configured to receive the first write gate control signal, and a second electrode connected to a first write output node; a second write output transistor comprising a control electrode configured to receive the second write gate control signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a second write output node; and a third output transistor comprising a control electrode connected to the first write output node, a first electrode connected to the second write output node, and a second electrode configured to receive a second clock signal, and a signal of the second write output node is the write gate signal.”;
“A display apparatus comprising: a display panel comprising a pixel; a gate emission driver configured to output a gate signal and an emission signal to the display panel; and a data driver configured to output a data voltage to the display panel, wherein: the gate emission driver comprises: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, the gate signal block is configured to: generate a carry signal and the gate signal based on a previous carry signal; and output the gate signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert the emission signal to an inverted emission signal; and an outputting determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the outputting determining circuit comprises: a first determining transistor comprising a control electrode configured to receive the emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first control node; a second determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the first control node, and a second electrode connected to a second control node; a third determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the second control node, and a second electrode connected to a third control node; and a fourth determining transistor comprising a control electrode configured to receive the inverted emission signal, a first electrode connected to the third control node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and the first determining transistor and the second determining transistor are each a P-type transistor, and the third determining transistor and the fourth determining transistor are each an N-type transistor.”; and
“An output control circuit comprising: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an outputting determining circuit configured to generate an output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the outputting determining circuit comprises: a first determining transistor comprising a control electrode configured to receive the emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first control node; a second determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the first control node, and a second electrode connected to a second control node; a third determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the second control node, and a second electrode connected to a third control node; and a fourth determining transistor comprising a control electrode configured to receive the inverted emission signal, a first electrode connected to the third control node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and the first determining transistor and the second determining transistor are each a P-type transistor and the third determining transistor and the fourth determining transistor are each an N-type transistor.”
Response to Arguments
Applicant’s arguments filed 3/19/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner recommends adding allowable subject matter to independent claims to advance prosecution.
Conclusion
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/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 9/16/2026
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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