DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10, 18, 20-22 and 24-28 are rejected under 35 U.S.C. 103 as being unpatentable over In et al. (US 2022/0238063 A1) in view of Chung (US 2007/0040786 A1).
As to claim 1, In teaches a gate emission driver comprising:
a gate signal block (see at least [0082] “the emission driver 300 may supply an emission control signal to the emission control lines ED to ELn”); and
the gate signal block comprises:
a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal (see at least [0215] “the first output terminal 105 of the first stage ST1 may be connected to the first input terminal 201 of the second stage ST2, ... The first carry signal CR1 of the high level H may be supplied to the third node N3 …. Similarly, the second carry signal CR2 .. may be supplied to the supplied third stage ST3); and
a second driver configured to output a gate signal based on the gate control signal (see at least [0222] “the output circuit 22”, [0224] “the second output voltage OUT2 of the high level H may be supplied to the first output terminal 205.”).
In does not directly teach an output control signal block configured to control an outputting of the gate signal block; and an output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal.
Chung teaches an output control signal block configured to control an outputting of the gate signal block (see at least [0075] “the emission control driver 16 includes a shift register 17 and a logical operation portion 22. The shift register 17 is connected to a plurality of flip-flops FF1, FF2, FF3, FF4, . . . shifting an input signal by one clock cycle and outputting the shifted signal. .. The logical operation portion 22 includes a plurality of logic gates … and generate emission control signals”); and
an output control signal block comprises:
an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least [0076] “The first flip-flop FF1 … outputs an output signal OUT1 and an inverted output signal OUTB1.”; [0085] “the flip-flop FF1 includes . two inverters INV1 and INV2.”; [0086] “the first inverter INV1 inverts the sampled signal and outputs the inverted signal.”); and
an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least [0080] The first logic gate OR1 receives the output signals OUT1 and OUTB1 .. and the output signals OUT2 and OUTB2 … . outputs a low-level emission control signal E1, only when the output signals OUT1 and OUT2 .. are at low levels and the inverted output signals OUTB1 and OUTB2 .. are at high levels”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine In and Chung because both are directed to gate/emission driving circuits for OLED display panels, and more particularly to controlling emission timing so as to prevent unintended emission and improve display stability. A person of ordinary skill in the art would have recognized that the inverter and logic-based emission control circuitry of Chung provides a known and predictable technique for gating the output of an emission driver in response to emission and enable signals, and that such circuitry could be applied to the gate signal block of In to further suppress unintended emission and improve operational stability, particularly during non-emission periods or initialization. The combination merely involves integrating known emission-gating logic (Chung) with a known carry-based emission driver (In), where each circuit performs the same function it was known to perform in the prior art—namely, generating emission signals (In) and selectively enabling or disabling those signals (Chung). Such integration represents the use of a known technique to improve a similar device in the same way, yielding predictable results, and does not require a change in the fundamental operation of In’s gate emission driver. Furthermore, emission drivers commonly include both analog driving stages and digital or logic-based control stages, and it would have been within the routine skill of a display driver circuit designer to incorporate inverter and logic circuitry upstream of an output stage to control signal output timing. Accordingly, one of ordinary skill in the art would have been motivated to combine In and Chung with a reasonable expectation of success.
As to claim 18, In teaches a display apparatus comprising:
a display panel comprising a pixel (see at least fig. 1: display panel 100 and pixel PX);
a gate emission driver configured to output a gate signal and an emission signal to the display panel (see at least fig. 1: timing controller 500, scan driver 200/emission driver 300 and [0076] “the scan driver 200 and the emission driver 300 may be defined by portions of a single gate driver.”); and
a data driver configured to output a data voltage to the display panel (see at least fig. 1: data driver 400),
wherein: the gate emission driver comprises:
a gate signal block (see at least [0082] “the emission driver 300 may supply an emission control signal to the emission control lines ED to ELn”);
the gate signal block is configured to:
generate a carry signal and the gate signal based on a previous carry signal (see at least [0215] “the first output terminal 105 of the first stage ST1 may be connected to the first input terminal 201 of the second stage ST2, ... The first carry signal CR1 of the high level H may be supplied to the third node N3 …. Similarly, the second carry signal CR2 .. may be supplied to the supplied third stage ST3); and
output the gate signal in response to an output control signal (see at least [0222] “the output circuit 22”, [0224] “the second output voltage OUT2 of the high level H may be supplied to the first output terminal 205.”).
In does not directly teach an output control signal block configured to control an outputting of the gate signal block, and the output control signal block comprises: an inverter circuit configured to convert the emission signal to an inverted emission signal; and an outputting determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal.
Chung teaches an output control signal block configured to control an outputting of the gate signal block (see at least [0075] “the emission control driver 16 includes a shift register 17 and a logical operation portion 22. The shift register 17 is connected to a plurality of flip-flops FF1, FF2, FF3, FF4, . . . shifting an input signal by one clock cycle and outputting the shifted signal. .. The logical operation portion 22 includes a plurality of logic gates … and generate emission control signals”); and
an output control signal block comprises:
an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least [0076] “The first flip-flop FF1 … outputs an output signal OUT1 and an inverted output signal OUTB1.”; [0085] “the flip-flop FF1 includes . two inverters INV1 and INV2.”; [0086] “the first inverter INV1 inverts the sampled signal and outputs the inverted signal.”); and
an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least [0080] The first logic gate OR1 receives the output signals OUT1 and OUTB1 .. and the output signals OUT2 and OUTB2 … . outputs a low-level emission control signal E1, only when the output signals OUT1 and OUT2 .. are at low levels and the inverted output signals OUTB1 and OUTB2 .. are at high levels”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine In and Chung because both are directed to gate/emission driving circuits for OLED display panels, and more particularly to controlling emission timing so as to prevent unintended emission and improve display stability. A person of ordinary skill in the art would have recognized that the inverter and logic-based emission control circuitry of Chung provides a known and predictable technique for gating the output of an emission driver in response to emission and enable signals, and that such circuitry could be applied to the gate signal block of In to further suppress unintended emission and improve operational stability, particularly during non-emission periods or initialization. The combination merely involves integrating known emission-gating logic (Chung) with a known carry-based emission driver (In), where each circuit performs the same function it was known to perform in the prior art—namely, generating emission signals (In) and selectively enabling or disabling those signals (Chung). Such integration represents the use of a known technique to improve a similar device in the same way, yielding predictable results, and does not require a change in the fundamental operation of In’s gate emission driver. Furthermore, emission drivers commonly include both analog driving stages and digital or logic-based control stages, and it would have been within the routine skill of a display driver circuit designer to incorporate inverter and logic circuitry upstream of an output stage to control signal output timing. Accordingly, one of ordinary skill in the art would have been motivated to combine In and Chung with a reasonable expectation of success.
As to claim 22, In teaches a circuit that generates and outputs a control signal (see at least [0222]–[0224]: an output circuit configured to output an output signal based on internal control signals).
In does not directly teach an inverter circuit configured to convert an emission signal to an inverted emission signal, and an output determining circuit configured to generate an output control signal based on an enable signal, the emission signal, and the inverted emission signal.
Chung teaches an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least [0076] “The first flip-flop FF1 … outputs an output signal OUT1 and an inverted output signal OUTB1.”; [0085] “the flip-flop FF1 includes . two inverters INV1 and INV2.”; [0086] “the first inverter INV1 inverts the sampled signal and outputs the inverted signal.”); and
an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least [0080] The first logic gate OR1 receives the output signals OUT1 and OUTB1 .. and the output signals OUT2 and OUTB2 … . outputs a low-level emission control signal E1, only when the output signals OUT1 and OUT2 .. are at low levels and the inverted output signals OUTB1 and OUTB2 .. are at high levels” – note the additional signal (OUT2/OUTB2) functions as an enable signal that controls generation of the output control signal.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of In to include the inverter circuit and output determining circuit taught by Chung. The inverter and output determining circuitry of Chung represents a known and predictable technique for generating an output control signal based on a signal, its inverted signal, and an enable signal. A person of ordinary skill in the art would have recognized that incorporating such circuitry into the circuit of In would provide controlled output signal generation in response to enable and signal conditions, yielding predictable results. The combination merely involves the use of a known output control technique (Chung) in a known circuit (In), where each element performs the same function it was known to perform in the prior art, and does not require a change in the fundamental operation of either reference.
As to claim 28, In teaches an electronic apparatus comprising:
a display panel comprising a pixel (see at least fig. 1: display panel 100 and pixel PX);
a gate emission driver configured to output a gate signal and an emission signal to the display panel (see at least fig. 1: scan driver 200/emission driver 300 and [0076] “the scan driver 200 and the emission driver 300 may be defined by portions of a single gate driver.”); and
a data driver configured to output a data voltage to the display panel (see at least fig. 1: data driver 400),
a driving controller configured to control the gate emission driver and the data driver based on an input control signal (see at least fig. 1: timing controller 500 and [0080] “The timing controller 500 may receive an input control ... The timing controller 500 may generate a first control signal SCS for controlling a driving timing of the scan driver 200, a second control signal ECS for controlling a driving timing of the emission driver 300, and a third control signal DCS for controlling a driving timing of the data driver 400, based on the input control signal, and may provide the first control signal SCS, the second control signal ECS, and the third control signal DCS to the scan driver 200, the emission driver 300, and the data driver 400, respectively.”); and
a processor configured to output the input control signal (see at least [0080] “The timing controller 500 may receive an input control signal and an input image signal from an image source such as an external graphic device.”);
wherein: the gate emission driver comprises:
a gate signal block (see at least [0082] “the emission driver 300 may supply an emission control signal to the emission control lines ED to ELn”);
the gate signal block is configured to:
generate a carry signal and the gate signal based on a previous carry signal (see at least [0215] “the first output terminal 105 of the first stage ST1 may be connected to the first input terminal 201 of the second stage ST2, ... The first carry signal CR1 of the high level H may be supplied to the third node N3 …. Similarly, the second carry signal CR2 .. may be supplied to the supplied third stage ST3); and
output the gate signal in response to an output control signal (see at least [0222] “the output circuit 22”, [0224] “the second output voltage OUT2 of the high level H may be supplied to the first output terminal 205.”).
In does not directly teach an output control signal block configured to control an outputting of the gate signal block, and the output control signal block comprises: an inverter circuit configured to convert the emission signal to an inverted emission signal; and an outputting determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal.
Chung teaches an output control signal block configured to control an outputting of the gate signal block (see at least [0075] “the emission control driver 16 includes a shift register 17 and a logical operation portion 22. The shift register 17 is connected to a plurality of flip-flops FF1, FF2, FF3, FF4, . . . shifting an input signal by one clock cycle and outputting the shifted signal. .. The logical operation portion 22 includes a plurality of logic gates … and generate emission control signals”); and
an output control signal block comprises:
an inverter circuit configured to convert an emission signal to an inverted emission signal (see at least [0076] “The first flip-flop FF1 … outputs an output signal OUT1 and an inverted output signal OUTB1.”; [0085] “the flip-flop FF1 includes . two inverters INV1 and INV2.”; [0086] “the first inverter INV1 inverts the sampled signal and outputs the inverted signal.”); and
an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal (see at least [0080] The first logic gate OR1 receives the output signals OUT1 and OUTB1 .. and the output signals OUT2 and OUTB2 … . outputs a low-level emission control signal E1, only when the output signals OUT1 and OUT2 .. are at low levels and the inverted output signals OUTB1 and OUTB2 .. are at high levels”).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine In and Chung because both are directed to gate/emission driving circuits for OLED display panels, and more particularly to controlling emission timing so as to prevent unintended emission and improve display stability. A person of ordinary skill in the art would have recognized that the inverter and logic-based emission control circuitry of Chung provides a known and predictable technique for gating the output of an emission driver in response to emission and enable signals, and that such circuitry could be applied to the gate signal block of In to further suppress unintended emission and improve operational stability, particularly during non-emission periods or initialization. The combination merely involves integrating known emission-gating logic (Chung) with a known carry-based emission driver (In), where each circuit performs the same function it was known to perform in the prior art—namely, generating emission signals (In) and selectively enabling or disabling those signals (Chung). Such integration represents the use of a known technique to improve a similar device in the same way, yielding predictable results, and does not require a change in the fundamental operation of In’s gate emission driver. Furthermore, emission drivers commonly include both analog driving stages and digital or logic-based control stages, and it would have been within the routine skill of a display driver circuit designer to incorporate inverter and logic circuitry upstream of an output stage to control signal output timing. Accordingly, one of ordinary skill in the art would have been motivated to combine In and Chung with a reasonable expectation of success.
As to claim 5, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection), wherein when the enable signal has a high level and the emission signal has a low level, the gate signal has an activation level (see In at least [0082], [0224], and [0212]: emission control signals causing activation of scan/emission outputs and Chung at least [0080], [0114]–[0119]: a logic gate outputs a low-level emission control signal only when defined logic conditions are satisfied, and outputs a high-level emission control signal otherwise). Note in Chung, when the relevant control condition is satisfied (corresponding to an enabled state and a low emission input), the emission control signal transitions to an active level that permits emission or gate operation. A person of ordinary skill in the art would have understood this low-level emission control signal to correspond to an activation level for enabling the associated gate or emission operation. Note applying expected logic-level results of applying known emission-control logic (Chung) to a known gate/emission driver architecture (In), would have predictably resulted in a gate emission driver exhibiting the claimed enable/emission signal behaviors.
As to claim 6, the combination of In and Chung teach the gate emission driver of claim 5 (see above rejection), wherein when the enable signal has the high level and the emission signal has the low level, the output control signal has a low level (see Chung at least [0080] “outputs a low-level emission control signal only when the output signals OUT1 and OUT2 are at low levels and the inverted output signals OUTB1 and OUTB2 are at high levels.” – note this condition corresponds to an enabled logic state in which emission is permitted, resulting in a low-level output control signal).
As to claim 7, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection), wherein when the enable signal has a low level and the emission signal has a high level, the gate signal has an inactivation level (see Chung at least [0062], [0071]: emission control signals turning emission on or off; [0080] “outputs a high-level emission control signal in all other cases” -note a disabled state would have been understood by a person of ordinary skill in the art as an inactivation level of the gate or emission signal).
As to claim 8, the combination of In and Chung teach the gate emission driver of claim 7 (see above rejection), wherein when the enable signal has the low level and the emission signal has the high level, the output control signal has a high level (see Chung at least [0080], [0119]: when the activation condition is not met, the logic gate outputs a high-level emission control signal).
As to claim 9, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection), wherein when the enable signal has a high level and the emission signal has a high level, the output control signal maintains a previous level (see In at least [0166] “maintain the voltage (that is, the high level H) of the second power VGH.”).
As to claim 10, the combination of In and Chung teach the gate emission driver of claim 1 (see above rejection), wherein when the enable signal has a low level and the emission signal has a low level, the output control signal maintains a previous level (see In at least [0189] “the voltage of the second node N2 may be maintained at the low level L.”).
As to claim 20, the combination of In and Chung teach the display apparatus of claim 18 (see above rejection), wherein: the gate emission driver further comprises an emission signal block, the gate signal block comprises a first gate signal block and a second gate signal block, the output control signal block comprises a first output control signal block and a second output control signal block, the emission signal block, the first gate signal block, and the first output control signal block are located on a first side, and the second gate signal block and the second output control signal block are located on a first side and a second side different from the first side (see In at least fig. 1: scan driver 200/emission driver 300).
As to claim 21, the combination of In and Chung teach the display apparatus of claim 20 (see above rejection), wherein the emission signal block is connected to the second output control signal block through an emission line (see In at least fig. 1: emission driver 300).
As to claim 24, the combination of In and Chung teach the output control circuit of claim 22 (see above rejection), wherein when the enable signal has a high level and the emission signal has a low level, the output control signal has a low level (see In at least [0082], [0224], and [0212]: emission control signals causing activation of scan/emission outputs and Chung at least [0080], [0114]–[0119]: a logic gate outputs a low-level emission control signal only when defined logic conditions are satisfied, and outputs a high-level emission control signal otherwise). Note in Chung, when the relevant control condition is satisfied (corresponding to an enabled state and a low emission input), the emission control signal transitions to an active level that permits emission or gate operation. Note applying expected logic-level results of applying known emission-control logic (Chung) to a known gate/emission driver architecture (In), would have predictably resulted in a gate emission driver exhibiting the claimed enable/emission signal behaviors.
As to claim 25, the combination of In and Chung teach the output control circuit of claim 22 (see above rejection), wherein when the enable signal has a low level and the emission signal has a high level, the output control signal has a high level (see Chung at least [0080], [0119]: when the activation condition is not met, the logic gate outputs a high-level emission control signal).
As to claim 26, the combination of In and Chung teach the output control circuit of claim 22 (see above rejection), wherein when the enable signal has a high level and the emission signal has a high level, the output control signal maintains a previous level (see In at least [0166] “maintain the voltage (that is, the high level H) of the second power VGH.”).
As to claim 27, the combination of In and Chung teach the output control circuit of claim 22 (see above rejection), wherein when the enable signal has a low level and the emission signal has a low level, the output control signal maintains a previous level (see In at least [0189] “the voltage of the second node N2 may be maintained at the low level L.”).
Allowable Subject Matter
Claims 2-4, 11-17, 19 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art of record teach:
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the output determining circuit comprises: a first determining transistor comprising a control electrode configured to receive the emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first control node; a second determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the first control node, and a second electrode connected to a second control node; a third determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the second control node, and a second electrode connected to a third control node; and a fourth determining transistor comprising a control electrode configured to receive the inverted emission signal, a first electrode connected to the third control node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and the first determining transistor and the second determining transistor are each a P-type transistor and the third determining transistor and the fourth determining transistor are each an N-type transistor.”;
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the gate signal comprises an initialization gate signal, the second driver comprises: a first initialization output transistor comprising a control electrode configured to receive the output control signal, a first electrode connected to a second initialization control node, and a second electrode connected to a third initialization node; a second initialization output transistor comprising a control electrode connected to the third initialization node, a first electrode configured to receive a first power voltage, and a second electrode connected to a fourth initialization node; and a third initialization output transistor comprising a control electrode connected to a first initialization control node, a first electrode connected to the fourth initialization node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and a signal of the fourth initialization node is the initialization gate signal.”;
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the gate signal comprises a compensation gate signal, the second driver comprises: a first compensation output transistor comprising a control electrode configured to receive the output control signal, a first electrode connected to a second compensation control node, and a second electrode connected to a third compensation node; a second compensation output transistor comprising a control electrode connected to the third compensation node, a first electrode configured to receive a first power voltage, and a second electrode connected to a fourth compensation node; and a third compensation output transistor comprising a control electrode connected to a first compensation control node, a first electrode connected to the fourth compensation node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and a signal of the fourth compensation node is the compensation gate signal.”;
“A gate emission driver comprising: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, wherein: the gate signal block comprises: a first driver configured to generate a gate control signal and a carry signal based on a previous carry signal; and a second driver configured to output a gate signal based on the gate control signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an output determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the gate signal comprises a write gate signal, and the gate control signal comprises a first write gate control signal and a second write gate control signal, the second driver comprises: a first write output transistor comprising a control electrode configured to receive the output control signal, a first electrode configured to receive the first write gate control signal, and a second electrode connected to a first write output node; a second write output transistor comprising a control electrode configured to receive the second write gate control signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a second write output node; and a third output transistor comprising a control electrode connected to the first write output node, a first electrode connected to the second write output node, and a second electrode configured to receive a second clock signal, and a signal of the second write output node is the write gate signal.”;
“A display apparatus comprising: a display panel comprising a pixel; a gate emission driver configured to output a gate signal and an emission signal to the display panel; and a data driver configured to output a data voltage to the display panel, wherein: the gate emission driver comprises: a gate signal block; and an output control signal block configured to control an outputting of the gate signal block, the gate signal block is configured to: generate a carry signal and the gate signal based on a previous carry signal; and output the gate signal in response to an output control signal, and the output control signal block comprises: an inverter circuit configured to convert the emission signal to an inverted emission signal; and an outputting determining circuit configured to generate the output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the outputting determining circuit comprises: a first determining transistor comprising a control electrode configured to receive the emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first control node; a second determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the first control node, and a second electrode connected to a second control node; a third determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the second control node, and a second electrode connected to a third control node; and a fourth determining transistor comprising a control electrode configured to receive the inverted emission signal, a first electrode connected to the third control node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and the first determining transistor and the second determining transistor are each a P-type transistor, and the third determining transistor and the fourth determining transistor are each an N-type transistor.”; and
“An output control circuit comprising: an inverter circuit configured to convert an emission signal to an inverted emission signal; and an outputting determining circuit configured to generate an output control signal based on an enable signal, the emission signal, and the inverted emission signal,
wherein: the outputting determining circuit comprises: a first determining transistor comprising a control electrode configured to receive the emission signal, a first electrode configured to receive a first power voltage, and a second electrode connected to a first control node; a second determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the first control node, and a second electrode connected to a second control node; a third determining transistor comprising a control electrode configured to receive the enable signal, a first electrode connected to the second control node, and a second electrode connected to a third control node; and a fourth determining transistor comprising a control electrode configured to receive the inverted emission signal, a first electrode connected to the third control node, and a second electrode configured to receive a second power voltage lower than the first power voltage, and the first determining transistor and the second determining transistor are each a P-type transistor and the third determining transistor and the fourth determining transistor are each an N-type transistor.”
Conclusion
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/JENNIFER L ZUBAJLO/ Examiner, Art Unit 2627 1/7/2026
/KE XIAO/ Supervisory Patent Examiner, Art Unit 2627