Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 7 February 2024. It is noted, however, that applicant has not filed a certified copy of the KR10-2024-0018958 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023.0260448) in view of Kim (US 2014.0028859).
Regarding claim 1, Lee disclose:
An electronic device comprising: a memory; a driving controller; a light emitting element (see Fig. 16-17, 20-21; [0121-0130, 0111-0115]; memory 1120 to store device operation instructions; driving controller 750; light emitting element EL)
a first transistor including a first electrode, a second electrode, and a gate electrode configured to receive a data signal; a second transistor connected between a first driving voltage line and the first electrode of the first transistor and configured to receive a first emission signal; and a third transistor connected between the second electrode of the first transistor and the light emitting element and configured to receive a second emission signal, wherein the first emission signal includes a compensation period and an emission period, and the memory stores instructions that, when executed by the driving controller, cause the driving controller (see Fig. 16-17, 20-21; [0121-0130, 0111-0115]; first TFT T1 to receive data signal DL; second TFT T7 to receive first emission signal EM2; third TFT T5 to receive second emission signal EM; where EM2 has a compensation period VCP and emission period EP)
While Lee at [0114] provides the compensation time VCP may be readily adjusted, it is not explicit as to, but is not explicit as to, but Kim disclose:
determine a compensation time of the compensation period depending on target luminance (see Fig. 1, 6; [0032-0033, 0131-0133]; where target luminance is used to determine compensation period of OLED).
Therefore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention, to combine the known techniques of Kim to that of Lee to predictably prevent grayscale stain and provide uniform luminance of the display ([0037]).
Regarding claim 2, the rejection of claim 1 is incorporated herein. Lee further disclose:
the first emission signal is at an active level for turning on the second transistor in each of the compensation period and the emission period (see Fig. 17).
Regarding claim 3, the rejection of claim 1 is incorporated herein. Kim further disclose:
when the target luminance has a first value, the compensation time of the compensation period is a first time, wherein when the target luminance has a second value, the compensation time of the compensation period is a second time, and wherein the memory stores instructions that, when executed by the driving controller, cause the driving controller to set the first time longer than the second time when the first value is greater than the second value (see Fig. 4; [0111-0112, 0127]; where depending on target luminance and measured luminance difference, the compensation time may vary (e.g., longer or shorter)).
Regarding claim 4, the rejection of claim 1 is incorporated herein. Lee further disclose:
a fourth transistor connected between the light emitting element and an initialization voltage line configured to receive an initialization voltage (see Fig. 16; fourth TFT T6 receiving initialization voltage Vint).
Regarding claim 5, the rejection of claim 4 is incorporated herein. Kim further disclose:
the memory stores instructions that, when executed by the driving controller, cause the driving controller to determine a voltage level of the initialization voltage depending on the target luminance and characteristics of the light emitting element (see Fig. 5; [0116-0122] variable Vint).
Regarding claim 6, the rejection of claim 1 is incorporated herein. Lee further disclose:
each of the first transistor, the second transistor, and the third transistor is an N-type transistor (see [0017]).
Regarding claim 7, claim 7 is rejected under the same rationale as claim 1, where Lee further disclose:
a display panel including a plurality of pixels, each of which is connected to a plurality of scan lines, a first emission line, a second emission line, and a data line; a scan driving circuit configured to output a plurality of scan signals to the plurality of scan lines; an emission driving circuit configured to output a first emission signal and a second emission signal to the first emission line and the second emission line, respectively; and a driving controller (see Fig. 20; [0123-0124]; pixels Px, scanlines G, emission lines EM/EM2; data lines DL; scan circuit 730; emission circuit 740; drive controller 750).
Regarding claims 8-9, claims 8-9 are rejected under the same rationale as claims 2-3.
Claim(s) 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023.0260448) in view of Kim (US 2014.0028859) in further view of Kim’042 (US 2022.0140042).
Regarding claim 10, the rejection of claim 7 is incorporated herein. Lee and Kim are not explicit as to, but Kim’042 disclose:
the plurality of pixels includes a first color pixel, a second color pixel, and a third color pixel (see [0055]).
Therefore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention, to combine the known techniques of Kim’042 to that of Lee and Kim to predictably provide a display with color images.
Regarding claim 11, the rejection of claim 10 is incorporated herein. Kim further disclose:
a voltage generator configured to generate a first initialization voltage provided to the first color pixel, a second initialization voltage provided to the second color pixel, and a third initialization voltage provided to the third color pixel, wherein the memory stores instructions that, when executed by the driving controller, cause the driving controller to determine a voltage level of each of the first initialization voltage, the second initialization voltage, and the third initialization voltage depending on the target luminance and luminance deviation between the first color pixel, the second color pixel, and the third color pixel (see Fig. 1, 5; [0116-0122]; voltage generator 140 variable initialization voltages depending on target luminaces of pixels; see also Kim’042 at [0055] for color pixels).
Regarding claim 12, claim 12 is rejected under the same rationale as claim 4.
Regarding claim 13, the rejection of claim 12 is incorporated herein. Lee further disclose
the first color pixel further includes: a fifth transistor connected between the data line and the gate electrode of the first transistor, and including a gate electrode connected to a first scan line of the plurality of scan lines; and a sixth transistor connected between a reference voltage line and the gate electrode of the first transistor and including a gate electrode connected to a second scan line of the plurality of scan lines (see Fig. 16; fifth TFT T2 and sixth TFT T3)
Regarding claim 14, the rejection of claim 12 is incorporated herein. Lee further disclose
the first color pixel further includes: a capacitor including a first electrode connected to the first gate electrode of the first transistor, and a second electrode; and a seventh transistor connected between the second electrode of the capacitor and a second initialization voltage line (see Fig. 16; capacitor Cst and seventh TFT T4)
Regarding claim 15, claim 15 is rejected under the same rationale as claim 6.
Regarding claim 16, Lee disclose:
An electronic device comprising: a memory; a driving controller; a display panel including pixels; wherein the memory stores instructions that, when executed by the driving controller, cause the driving controller execute device functionality (see Fig. 16-17, 20-21; [0121-0130, 0111-0115]; memory 1120 to store device operation instructions; driving controller 750; display panel with pixels)
Lee is not explicit as to, but Kim disclose:
a voltage generator configured to generate a first initialization voltage provided to the first color pixel, a second initialization voltage provided to the second color pixel, and a third initialization voltage provided to the third color pixel, determine a voltage level of each of the first initialization voltage, the second initialization voltage, and the third initialization voltage depending on target luminance and luminance deviation between the first color pixel, the second color pixel, and the third color pixel (see Fig. 1, 4, 6; [0032-0033, 0082, 0107, 0131-0133]; voltage generator 140 to provide first through third initialization voltages to first through third pixels, where target luminance is measured and luminance deviation (threshold voltages) are used to determine the initialization voltages in order to compensate luminance; see Lee for memory and driving controller).
Therefore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention, to combine the known techniques of Kim to that of Lee to predictably prevent grayscale stain and provide uniform luminance of the display ([0037]).
Lee and Kim are not explicit as to, but Kim’042 disclose:
a display panel including a first color pixel, a second color pixel, and a third color pixel (see [0055]).
Therefore, it would have been obvious to one of ordinary skill in the art, prior to the effective filing date of applicant’s invention, to combine the known techniques of Kim’042 to that of Lee and Kim to predictably provide a display with color images.
Regarding claim 17, the rejection of claim 16 is incorporated herein. Lee further disclose:
a first transistor including a first electrode, a second electrode, and a gate electrode configured to receive a data signal; a second transistor connected between a first driving voltage line and the first electrode of the first transistor and configured to receive a first emission signal; a third transistor connected between the second electrode of the first transistor and the light emitting element and configured to receive a second emission signal; and a fourth transistor connected between the light emitting element and an initialization voltage line configured to receive the first initialization voltage (see Fig. 16; first TFT T1 to receive data signal DL; second TFT T7 to receive first emission signal EM2; third TFT T5 to receive second emission signal EM; fourth TFT T6 receiving initialization voltage Vint)
Kim’042 further disclose:
the first color pixel includes: a light emitting element configured to emit first color light (see [0055])
Regarding claim 18, the rejection of claim 17 is incorporated herein. Lee as modified by Kim further disclose:
the first emission signal includes a compensation period and an emission period, and the memory stores instructions that, when executed by the driving controller, cause the driving controller to determine a compensation time of the compensation period depending on the target luminance (see Lee Fig. 16-17, 20-21; [0121-0130, 0111-0115]; memory 1120 to store device operation instructions; driving controller 750; see also Kim Fig. 1, 6; [0032-0033, 0131-0133]; where target luminance is used to determine compensation period of OLED)
Regarding claims 19-20, claims 19-20 are rejected under the same rationale as claims 2-3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH BUKOWSKI whose telephone number is (571)270-7913. The examiner can normally be reached Monday - Friday // 0730-1530.
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/kenneth bukowski/ Primary Examiner, Art Unit 2621