DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claims 1-20 are pending in this office action. Claims 9-13 and 18-20 are withdrawn. Claims 1-8 and 14-17 are presented for examination.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
The abstract is not within the range of 50 to 150 words in length.
The abstract does not end with a period.
In paragraph [0029], line 13, “stored a location” should be “stored at a location”.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “PROCESSOR WITH INSTRUCTION CONCATENATION WITH A FIRST INSTRUCTION THAT SPECIFIES WHETHER TO EXECUTE A SECOND INSTRUCTION PRIOR TO THE FIRST INSTRUCTION”
Drawings
The drawings are objected to because:
All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. However, the drawings in the file wrapper do not meet this requirement — see, for example, the array of white dots that causes the lines, text, and numbers to appear fuzzy and blurry. This may be caused by dithering being applied when a conversion from greyscale to black has taken place; if so, Examiner recommends ensuring that any drawings to be filed do not contain any grey elements.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5 and 14-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5 and 19 of U.S. Patent No. 12153929 in view of Moyer et al. (Moyer) (US 20080040591 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because, for any limitations that are not explicitly or implicitly disclosed by claims 5 and 19 of U.S. Patent No. 12153929, Moyer is relied upon to render obvious these additional limitations in an analogous manner as Moyer is relied upon in the rejections of the aforementioned instant claims below; see the citations of Moyer and corresponding rationales for obviousness in the rejections of the aforementioned instant claims under 35 USC 103 below.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5 and 19 of U.S. Patent No. 12153929 and Moyer as applied to claim 3 above, and further in view of Uhler et al. (US 5500947). Regarding the additional limitations that instant claim 6 recites that are not taught by the combination thus far, Uhler is relied upon to render obvious these additional limitations in an analogous manner as Uhler is relied upon in the rejection of the aforementioned instant claim below; see the citations of Uhler and corresponding rationale for obviousness in the rejection of the aforementioned instant claim under 35 USC 103 below.
Claims 7-8 and 17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5 and 19 of U.S. Patent No. 12153929 and Moyer as applied to claims 1 and 14 above, and further in view of Owen et al. (Owen) (US 20040088704 A1) .
Regarding the additional limitations of instant claims 7-8 and 17 that are not taught by the combination thus far, Owen is relied upon to render obvious these additional limitations in an analogous manner as Owen is relied upon in the rejections of the aforementioned instant claims below; see the citations of Owen and corresponding rationale for obviousness in the rejections of the aforementioned instant claims under 35 USC 103 below.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 14-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. See MPEP 2106.
Regarding Eligibility Step 1, each of the claims is directed to a process, machine, manufacture, or composition of matter. Specifically, each of the claims is directed to a process.
Regarding Eligibility Step 2A, Prong One, each of the claims recites abstract ideas. Specifically, each of the claims recites mental processes that can be performed in the human mind, or by a human using a pen and paper. For example, claim 14 recites “A method comprising: receiving a first instruction; thereafter, receiving a second instruction, wherein the first instruction specifies whether to execute the second instruction prior to the first instruction; determining whether to execute the second instruction prior to the first instruction; and executing the first instruction and the second instruction.” Examiner notes that a person may receive a first written or oral instruction which specifies performing a second instruction being performing the first instruction. For example, a student may receive an instruction to complete all test questions but to wait to do so until after an instruction is received by the test proctor to begin the test.
Regarding Eligibility Step 2A, Prong Two, the claim as a whole does not integrate the judicial exception into a practical application. In other words, the claim does not recite additional elements that integrate the judicial exception into a practical application.
Regarding Eligibility Step 2B, the claim does not recite additional elements that amount to an inventive concept. In other words, the claim does not recite additional elements that, individually or in combination, amount to significantly more than the judicial exception itself.
Claims 15-16 merely limit the particulars of the recited instruction, and thus does not recite additional elements which could integrate the abstract idea into a practical application or provide significantly more than the abstract idea itself.
Claim 17 merely reflects further abstract ideas including mental processes in an analogous manner as claim 14 above.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 14-16 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Smith et al. (Smith) (US 6311266 B1) in view of Moyer et al. (Moyer) (US 20080040591 A1).
Consider claim 1, Smith discloses a processor (col. 1, lines 23-24, a computer system is organized to permit execution of multiple instructions) comprising: an instruction fetch unit configured to: retrieve a first instruction (col. 5, line 27, current instruction); and retrieve a second instruction subsequent to the retrieving of the first instruction (col. 5, line 26, subsequent instructions), wherein the first instruction specifies whether to execute the second instruction prior to the first instruction or subsequent to the first instruction; and an execution unit coupled to the instruction fetch unit and configured to, based on the first instruction specifying that the second instruction is to be executed prior to the first instruction, execute the second instruction prior to the first instruction (col. 5, lines 25-28, the value of the code stored as the increment code represents the number of subsequent instructions whose execution can begin before the current instruction has completed its own execution; col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34; col. 1, lines 47-50, the subsequent instruction in the set can start execution and, in fact, can complete its execution prior to the previous instruction having completed its execution).
To any extent to which Smith does not inherently disclose a processor, an instruction fetch unit configured to retrieve the first instruction and the second instruction subsequent to retrieving the first instruction, and an execution unit coupled to the instruction fetch unit, Moyer explicitly discloses a processor ([0018], line 7, processor), an instruction fetch unit configured to retrieve a first instruction and a second instruction subsequent to retrieving the first instruction ([0022], lines 1-4, fetch unit 29 provides fetch addresses to a memory, such as system memory 14, and in return, receives data, such as fetched instructions, which may be stored into instruction buffer 23 and then provided to IR 25), and an execution unit coupled to the instruction fetch unit ([0020], line 8, execution unit 34), and it would have been obvious to one of ordinary skill in the art at the time of the invention to combine the teaching of Moyer with the invention of Smith in order to facilitate performance of the instruction. Alternatively, this modification merely entails combining prior art elements (the teachings of Smith cited above, and the well-known processing components explicitly disclosed by Moyer) according to known methods (Examiner submits that a processor, the use of an instruction fetch unit, and the use of an execution unit, were well-known at the time of the invention, as reflected by Moyer) to yield predictable results (the invention of Smith, entailing a processor, an instruction fetch unit configured to retrieve the first instruction and the second instruction subsequent to retrieving the first instruction, and an execution unit coupled to the instruction fetch unit), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 2, the combination thus far entails the processor of claim 1 (see above), wherein the first instruction specifies whether to execute the second instruction prior to the first instruction or subsequent to the first instruction (Smith, col. 5, lines 25-28, the value of the code stored as the increment code represents the number of subsequent instructions whose execution can begin before the current instruction has completed its own execution; col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34; col. 1, lines 47-50, the subsequent instruction in the set can start execution and, in fact, can complete its execution prior to the previous instruction having completed its execution). However, the combination thus far does not entail that an opcode included in the first instruction is that which performs the aforementioned specification.
On the other hand, Moyer further discloses the well-known concept of an instruction specification being implemented as part of the opcode, or separate from the opcode, as alternatives (FIG. 3, which shows the specifier 50 being distinct from the opcode 42; [0026], lines 32-34, which discloses that in an alternative embodiment, specifier 50 may be included or encoded as part of opcode 42).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine the further teaching of Moyer with the previously explained combination of Smith and Moyer in order to save non-opcode space. Alternatively, this modification merely entails combining prior art elements (the prior art elements of the previously explained combination of Smith and Moyer, and Moyer’s further teaching of an instruction specification being implemented as part of the opcode) according to known methods (Moyer as cited explicitly an instruction specification being implemented as part of the opcode, and Examiner further generally submits that use of an opcode field to specify behavior is known) to yield predictable results (the previously explained combination of Smith and Moyer, wherein an opcode included in the first instruction is that which performs the aforementioned specification), which is an example of a rationale that may support a conclusion of obviousness, as set forth in MPEP 2143. Alternatively, this modification merely entails simple substitution of one known element (an instruction specification being implemented separate from the opcode) for another (an instruction specification being implemented as part of the opcode) to obtain predictable results (Moyer discloses the two aforementioned known elements as alternatives, and in both cases, instruction specification occurs), which is an example of a rationale that may support a conclusion of obviousness, as set forth in MPEP 2143.
Consider claim 3, the overall combination entails the processor of claim 1 (see above), wherein: the first instruction includes an opcode (Smith, col. 5, lines 11-13, this instruction may include such operations as a memory operation 36, an arithmetic operation 38, or a control operation 40. Each instruction may have all three of these types of operations, or only two or only one of these types of operations) and a field distinct from the opcode; and the field specifies whether to execute the second instruction prior to the first instruction or subsequent to the first instruction (Smith, col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34).
Consider claim 4, the overall combination entails the processor of claim 3 (see above), wherein the field specifies a number of instructions subsequent to the first instruction that are to be executed prior to the first instruction (Smith, col. 5, lines 25-28, the value of the code stored as the increment code represents the number of subsequent instructions whose execution can begin before the current instruction has completed its own execution; col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34; col. 1, lines 47-50, the subsequent instruction in the set can start execution and, in fact, can complete its execution prior to the previous instruction having completed its execution).
Consider claim 5, the overall combination entails the processor of claim 4 (see above), wherein the field further specifies a location at which the instructions subsequent to the first instruction that are to be executed prior to the first instruction are stored (Smith, col. 5, lines 25-28, the value of the code stored as the increment code represents the number of subsequent instructions whose execution can begin before the current instruction has completed its own execution; col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34; col. 1, lines 47-50, the subsequent instruction in the set can start execution and, in fact, can complete its execution prior to the previous instruction having completed its execution).
Consider claim 14, Smith discloses a method comprising: receiving a first instruction (col. 5, line 27, current instruction); thereafter, receiving a second instruction (col. 5, line 26, subsequent instructions), wherein the first instruction specifies whether to execute the second instruction prior to the first instruction; determining whether to execute the second instruction prior to the first instruction; and executing the first instruction and the second instruction (col. 5, lines 25-28, the value of the code stored as the increment code represents the number of subsequent instructions whose execution can begin before the current instruction has completed its own execution; col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34; col. 1, lines 47-50, the subsequent instruction in the set can start execution and, in fact, can complete its execution prior to the previous instruction having completed its execution).
To any extent to which Smith does not inherently disclose receiving the first instruction and thereafter receiving the second instruction, Moyer explicitly receiving the first instruction and thereafter receiving the second instruction ([0022], lines 1-4, fetch unit 29 provides fetch addresses to a memory, such as system memory 14, and in return, receives data, such as fetched instructions, which may be stored into instruction buffer 23 and then provided to IR 25), and it would have been obvious to one of ordinary skill in the art at the time of the invention to combine the teaching of Moyer with the invention of Smith in order to facilitate performance of the instruction. Alternatively, this modification merely entails combining prior art elements (the teachings of Smith cited above, and the well-known processing behavior explicitly disclosed by Moyer) according to known methods (Examiner submits that the use of an instruction fetch unit was well-known at the time of the invention, as reflected by Moyer) to yield predictable results (the invention of Smith, entailing receiving the first instruction and thereafter receiving the second instruction), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 15, the combination thus far entails the method of claim 14 (see above), wherein the first instruction specifies whether to execute the second instruction prior to the first instruction (Smith, col. 5, lines 25-28, the value of the code stored as the increment code represents the number of subsequent instructions whose execution can begin before the current instruction has completed its own execution; col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34; col. 1, lines 47-50, the subsequent instruction in the set can start execution and, in fact, can complete its execution prior to the previous instruction having completed its execution). However, the combination thus far does not entail that an opcode included in the first instruction is that which performs the aforementioned specification.
On the other hand, Moyer further discloses the well-known concept of an instruction specification being implemented as part of the opcode, or separate from the opcode, as alternatives (FIG. 3, which shows the specifier 50 being distinct from the opcode 42; [0026], lines 32-34, which discloses that in an alternative embodiment, specifier 50 may be included or encoded as part of opcode 42).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine the further teaching of Moyer with the previously explained combination of Smith and Moyer in order to save non-opcode space. Alternatively, this modification merely entails combining prior art elements (the prior art elements of the previously explained combination of Smith and Moyer, and Moyer’s further teaching of an instruction specification being implemented as part of the opcode) according to known methods (Moyer as cited explicitly an instruction specification being implemented as part of the opcode, and Examiner further generally submits that use of an opcode field to specify behavior is known) to yield predictable results (the previously explained combination of Smith and Moyer, wherein an opcode included in the first instruction is that which performs the aforementioned specification), which is an example of a rationale that may support a conclusion of obviousness, as set forth in MPEP 2143. Alternatively, this modification merely entails simple substitution of one known element (an instruction specification being implemented separate from the opcode) for another (an instruction specification being implemented as part of the opcode) to obtain predictable results (Moyer discloses the two aforementioned known elements as alternatives, and in both cases, instruction specification occurs), which is an example of a rationale that may support a conclusion of obviousness, as set forth in MPEP 2143.
Consider claim 16, the overall combination entails the method of claim 14 (see above), wherein: the first instruction includes an opcode (Smith, col. 5, lines 11-13, this instruction may include such operations as a memory operation 36, an arithmetic operation 38, or a control operation 40. Each instruction may have all three of these types of operations, or only two or only one of these types of operations) and a field distinct from the opcode; and the field specifies whether to execute the second instruction prior to the first instruction (Smith, col. 4, lines 40-42, as part of each instruction, also stored in the same register is … an increment code 34).
Claim 6 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Smith and Moyer as applied to claim 3 above, and further in view of Uhler et al. (US 5500947).
Consider claim 6, the combination thus far entails the processor of claim 3 (see above) and a number of instructions subsequent to the first instruction that are to be executed prior to the first instruction, wherein the field of the first instruction specifies the number (Smith, col. 5, lines 11-13, this instruction may include such operations as a memory operation 36, an arithmetic operation 38, or a control operation 40. Each instruction may have all three of these types of operations, or only two or only one of these types of operations), but does not entail that the aforementioned processor further comprises a register configured to store the aforementioned number, wherein the aforementioned field of the first instruction specifies the register.
On the other hand, Uhler discloses a processor further comprises a register to store an operand, wherein a field of a first instruction specifies the register (col. 3, lines 11-14, a register addressing mode requires no main memory accesses, since the operand is stored in a CPU register which is specified in the machine-level instruction) as an alternative to immediate addressing (col. 3, lines 1-14, in order to reference a large range of locations in the specification of operands, the instruction sets of most computers support a variety of different methods, called addressing modes, for indicating the effective address of operands in a machine-level instruction. The simplest method of specifying an operand in a machine-level instruction is immediate or literal addressing, in which the value of the operand is included in the machine-level instruction itself. This mode is useful in defining constants and initial values of variables, and no main memory references are needed to obtain the operand. Likewise, a register addressing mode requires no main memory accesses, since the operand is stored in a CPU register which is specified in the machine-level instruction).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine the teaching of Uhler with the combination of Smith and Moyer in order to save instruction space in instances where the immediate data size is greater than the register identifier size. Alternatively, this modification merely entails combining prior art elements (the prior art elements of the combination of Smith and Moyer, and Uhler’s teaching of register addressing) according to known methods (as noted by Uhler, the instruction sets of most computers support a variety of different addressing modes, including immediate addressing and register addressing) to yield predictable results (the combination of Smith and Moyer, wherein the field specifies a register storing the number rather than the number itself), which is an example of a rationale that may support a conclusion of obviousness, as set forth in MPEP 2143. Alternatively, this modification merely entails simple substitution of one known element (immediate addressing) for another (register addressing) to obtain predictable results (Uhler discloses the two aforementioned addressing modes as alternatives, and in both cases, an operand is specified), which is an example of a rationale that may support a conclusion of obviousness, as set forth in MPEP 2143.
Claims 7-8 and 17 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Smith and Moyer as applied to claims 1 and 14 above, and further in view of Chung et al. (Chung) (US 20100205408 A1) in view of Owen et al. (Owen) (US 20040088704 A1).
Consider claim 7, the combination thus far discloses the processor of claim 1 (see above), but does not disclose that the first instruction further specifies whether execution of the first instruction and the second instruction is to be atomic; and the execution unit is configured to, based on the first instruction specifying that the execution of the first instruction and the second instruction is to be atomic, disable interruption during the execution of the first instruction and the second instruction.
On the other hand, Chung discloses specifying atomicity in general, as well as a first instruction further specifying whether execution of a first instruction and a second instruction is to be atomic ([0028], lines 1-6, the processor may determine which of the instructions are speculative based, at least in part, on a prefix (a "speculative instruction prefix") that indicates that a particular instruction is to be executed speculatively (e.g., within a single atomic memory transaction); also note that when a prefix indicates that a second instruction is to be within a single atomic memory transaction, a prefix indicating that a first instruction is to be within the single atomic memory transaction specifies that execution of the first instruction and the second instruction is to be atomic).
Chung’s teaching facilitates decreased consumption of transactional memory hardware resources (Chung, [0030], lines 10-12) and supports atomic execution.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to combine the teaching of Chung with the combination of Smith and Moyer in order to decrease consumption of transactional memory hardware resources and support atomic execution. Note that Chung’s teaching of specifying atomicity, when applied to the combination of Smith and Moyer which entails a first instruction specifying execution behavior with respect to the first and a second instruction, results in the first instruction further specifying whether execution of the first instruction and the second instruction is to be atomic.
However, the combination thus far does not entail that the execution unit is configured to, based on the first instruction specifying that the execution of the first instruction and the second instruction is to be atomic, disable interruption during the execution of the first instruction and the second instruction.
On the other hand, Owen discloses based on execution of instructions being atomic, disabling interruption during the execution of the instructions ([0007], lines 22-24, the simplest way to achieve an atomic transaction is to disable interrupts once a process enters the critical section).
Owen’s teaching is a simple way to achieve an atomic transaction (Owen, [0007], lines 22-24) and easy to implement (Owen, [0007], lines 25-26).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to combine the teaching of Owen with the combination of Smith, Moyer, and Chung in order to implement the atomic transaction in a simple and easy manner.
Consider claim 8, the overall combination entails the processor of claim 7 (see above), wherein the first instruction specifies an event that determines whether the execution of the first instruction and the second instruction is to be atomic (Chung, [0028], lines 1-6, the processor may determine which of the instructions are speculative based, at least in part, on a prefix (a "speculative instruction prefix") that indicates that a particular instruction is to be executed speculatively (e.g., within a single atomic memory transaction); also note that when a prefix indicates that a second instruction is to be within a single atomic memory transaction, a prefix indicating that a first instruction is to be within the single atomic memory transaction specifies that execution of the first instruction and the second instruction is to be atomic).
Consider claim 17, the combination thus far discloses the method of claim 14 (see above), but does not disclose that the first instruction specifies whether to execute the first instruction and the second instruction atomically; and the method further comprises determining whether to disable interruption during the executing of the first instruction and the second instruction based on whether the first instruction specifies to execute the first instruction and the second instruction atomically.
On the other hand, Chung discloses specifying atomicity in general, as well as a first instruction specifying whether to execute a first instruction and a second instruction atomically ([0028], lines 1-6, the processor may determine which of the instructions are speculative based, at least in part, on a prefix (a "speculative instruction prefix") that indicates that a particular instruction is to be executed speculatively (e.g., within a single atomic memory transaction); also note that when a prefix indicates that a second instruction is to be within a single atomic memory transaction, a prefix indicating that a first instruction is to be within the single atomic memory transaction specifies that execution of the first instruction and the second instruction is to be atomic).
Chung’s teaching facilitates decreased consumption of transactional memory hardware resources (Chung, [0030], lines 10-12) and supports atomic execution.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to combine the teaching of Chung with the combination of Smith and Moyer in order to decrease consumption of transactional memory hardware resources and support atomic execution. Note that Chung’s teaching of specifying atomicity, when applied to the combination of Smith and Moyer which entails a first instruction specifying execution behavior with respect to the first and a second instruction, results in the first instruction specifying whether to execute the first instruction and the second instruction atomically.
However, the combination thus far does not entail determining whether to disable interruption during the executing of the first instruction and the second instruction based on whether the first instruction specifies to execute the first instruction and the second instruction atomically.
On the other hand, Owen discloses disabling interruption during the execution of instructions based on the instructions being specified to execute atomically ([0007], lines 22-24, the simplest way to achieve an atomic transaction is to disable interrupts once a process enters the critical section).
Owen’s teaching is a simple way to achieve an atomic transaction (Owen, [0007], lines 22-24) and easy to implement (Owen, [0007], lines 25-26).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to combine the teaching of Owen with the combination of Smith, Moyer, and Chung in order to implement the atomic transaction in a simple and easy manner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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