Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 32, 42 and 51
b. Pending: 32-51
Claims 1-31 have been canceled and claims 32-51 have been newly added by preliminary amendments.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
Applicant's election with traverse of claims 32-41 (Group I) in the reply filed on 8/28/2026 is acknowledged. The traversal is on the ground(s) that these three groups are not patentably distinct.
Examiner rejects only Group I claims. Since the other two Groups namely Group II and Group III are not patentably distinct from Group I, by Applicant’s own admission, same rejection is applicable to Group II and Group III as well.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 11/25/2024 and 2/13/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Nonvolatile memory device and operating method with zone voltage generator.
Claim Objections
Claim 41 is objected to because of the following informalities: “control logic setts…”. Examiner suggests “control logic sets…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 32-41 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 32 is generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors. Last limitation of independent claim 32 recites:
“the zone voltage generator includes regulators configured to share an operational amplifier, to sequentially output corresponding feedback voltages to the operational amplifier to generate the zone voltages, and to apply the zone voltages to corresponding zones”. It is unclear what is meant by configured to share an operational amplifier. Does it mean regulators are generating sequential output for the operational amplifier? Input and output relationship needs to be clarified so that metes and bounds of the claim can be determined.
All the dependent claims 33-41 carry the same deficit and henceforth are rejected.
Claim 37 recites “a common phase of regulators sharing an operational amplifier”. For same above mentioned reason, claim 37 is rejected.
Claims 38-41 all depend on claim 37 directly or indirectly and carry the same deficit and henceforth are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 32-35 and 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Gangasani et al. (US 20170117054) in view of Wang et al. (US 20130010536).
Regarding independent claim 32, Gangasani discloses a storage device (Figs. 1-20), comprising:
at least one nonvolatile memory device (nonvolatile memory 100; Fig. 20); and
a controller configured to control the at least one nonvolatile memory device (memory controller 200 for controlling the nonvolatile memory 100; Fig. 20 and [0114]);
wherein the at least one nonvolatile memory device includes:
a plurality of memory blocks having a plurality of pages connected to wordlines and bitlines (Fig. 20 and [0115] describes nonvolatile memory device 100 may include a plurality of blocks BLK1 to BLKz (z being an integer greater than or equal to 2). Each of the blocks BLK1 to BLKz may include a plurality of pages 1 to m (m bring an integer greater than or equal to 2). [0044] describes Each of the memory blocks BLK1 to BLKz may be connected to the address decoder circuit 120 through a plurality of word lines WLs, at least one string selection line SSL(s), and at least one ground selection line GSL(s) and may be connected to the input/output circuit 140 through a plurality of bit lines BLs);
a zone voltage generator configured to generate zone voltages corresponding to zones in which the wordlines are divided into a plurality of areas (Fig. 19 and [0113] describes a plurality of zone-voltage generators 138-1 to 138-k may generate linear voltages applied to corresponding zones, respectively. Zone-voltage generator 138-1 may include a Vz1_1 generating unit and VZ1_2 generating unit to respectively generate voltages VZ1_1 and Vz1_2. Zone-voltage generators 138-2 through 138_k may be similarly configured. Claim 14 recites that word lines are divided into a plurality of zones, the voltage generating circuit further comprises a plurality of zone-voltage generators corresponding to the plurality of zones, each of the zone-voltage generators configured to generate word line voltages that are applied to word lines of a corresponding zone, and at least one of the zone-voltage generators comprises a linear voltage generator); and
a control logic configured to control the zone voltage generator during a programming operation, a read operation, or an erase operation (Fig. 20 and [0116] describes that during a program/read/erase operation, the control logic 150 may control the linear voltage generator 132 in response to external/internal environment information or a signal generated in hardware/firmware/software, so as to generate and/or apply linear voltages. In this case, as described FIGS. 1 to 19, the line voltage generator 132 may be applied to all or a portion of adjacent word lines and may generate word line voltages which linearly increase or decrease), and
the zone voltage generator (Fig. 5 and [0073] describes voltage generating unit 132-1) includes regulators configured to share an operational amplifier (Fig. 5 and [0073] describes an amplifier AMP), to sequentially output corresponding feedback voltages to the operational amplifier to generate the zone voltages, and to apply the zone voltages to corresponding zones (Figs. 4-5 and [0073]-[0077]).
Wang explicitly teaches regulators configured to share an operational amplifier (Fig. 4 and [0043] describes that regulator may include: an operational amplifier OP, an output P-type transistor, a first resistor and second resistor connected in serial, wherein the operational amplifier OP has an output terminal connected to a gate electrode of the output P-type transistor, a first input terminal connected to the reference voltage Vref, and a second input terminal connected to a feedback voltage Vfb, wherein the feedback voltage Vfb is led out from the connecting point of the first and the second resistors, or in other words, the second input terminal of the operational amplifier OP is connected between the first and the second resistors).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Wang to Gangasani in order to provide with word-line voltage regulating circuit as taught by Wang ([0002]).
Regarding claim 33, Gangasani and Wang together disclose all the elements of claim 32 as above and through Gangasani further each of the regulators is set to a target level by simultaneously dividing an input voltage during a set-up period (Figs. 4-5 and [0067], [0070] describes voltage source lines S1 to Sm may respectively have voltages, which linearly increase or decrease, for example, linear word line voltages Vwl_1 to Vwl_m by dividing a voltage between the first voltage V1 and the second voltage V2 using the resistor string RS).
Regarding claim 34, Gangasani and Wang together disclose all the elements of claim 33 as above and through Wang further the regulators perform regulation using the operational amplifier to sequentially generate corresponding output voltages during a regulation period (Figs. 3-4 and [0043] describes regulator used in the voltage supply circuit may include: an operational amplifier OP).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Wang to modified Gangasani in order to provide with word-line voltage regulating circuit as taught by Wang ([0002]).
Regarding claim 35, Gangasani and Wang together disclose all the elements of claim 34 as above and through Gangasani further reference voltages corresponding to the regulators vary during the regulation period (Fig. 5 and [0074] describes the resistor string 132-1a may be implemented with a variable resistor. Vdiv node of AMP is connected to the variable resistor output).
Regarding claim 37, Gangasani and Wang together disclose all the elements of claim 32 as above and through Gangasani further the control logic (150; Fig. 20) sets a common phase of regulators sharing an operational amplifier by dividing an input voltage, sets each divided phase of the regulators using the operational amplifier to generate an output voltage, and applies output voltages of the regulators corresponding to wordline areas (Fig. 19 shows for example signals S1, S2 etc., are generated by dividing an input voltage and meant for corresponding wortdline areas).
Regarding claim 38, Gangasani and Wang together disclose all the elements of claim 37 as above and through Wang further the control logic receives a common signal for simultaneously enabling the regulators, and outputs feedback signals corresponding to each of the regulators in response to the common signal ([0007] describes that during active mode, an activate signal SEN is inputted into the active word-line voltage regulator to activate the active word-line voltage regulator, so that the active word-line voltage regulator adjusts the output voltage of the charge pump).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Wang to modified Gangasani in order to provide with word-line voltage regulating circuit as taught by Wang ([0002]).
Claims 36 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Gangasani et al. (US 20170117054) in view of Wang et al. (US 20130010536) and Giese et al. (US 20160256874).
Regarding claim 36, Gangasani and Wang together disclose all the elements of claim 34 as above and through Giese further the zone voltage generator discharges output voltages corresponding to the regulators at the target level during the regulation period ([0058] describes high voltage discharges occur closer to a target value defined by the reference value it is compared with).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Giese to modified Gangasani in order to provide with high voltage discharges and arrangements for conducting these methods as taught by Giese ([0004]).
Regarding claim 41, Gangasani and Wang together disclose all the elements of claim 37 as above and through Giese further the control logic setts the divided phase includes sequentially discharging from a target level to the output voltages corresponding to the regulators in response to feedback signals ([0058] describes high voltage discharges occur closer to a target value defined by the reference value it is compared with).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Giese to modified Gangasani in order to provide with high voltage discharges and arrangements for conducting these methods as taught by Giese ([0004]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 9/15/2026
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