CTNF 18/958,291 CTNF 88495 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 2 – 21 are pending. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claim(s) 2 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1 of copending Application No. 17/984,332. Although the claims at issue are not identical, they are not patentably distinct from each other because they encompass substantially similar subject matter. This is a provisional nonstatutory double patenting rejection. The following table is presented for the purpose of a comparison of the conflicting claims between the applications. Application No. 18/958,291 Application No. 17/984,332 Claim 2 Claim 1 A failure detector for detecting an abnormality in a temperature complementary voltage, comprising: a first bipolar junction transistor in which a base and a collector are grounded; a current source configured to generate a bias current; a first resistor coupled between the current source and the emitter of the first bipolar junction transistor to generate an upper limit reference voltage; a second resistor and a third resistor configured to divide a first base-emitter voltage of the first bipolar junction transistor to generate a lower limit reference voltage; a first comparator configured to compare the temperature complementary voltage with the upper limit reference voltage to generate a first failure signal; and a second comparator configured to compare the temperature complementary voltage with the lower limit reference voltage to generate a second failure signal. A semiconductor device, comprising: a voltage generator configured to generate a first base-emitter voltage of a first bipolar junction transistor; and a failure detector configured to generate a failure signal by comparing the first base-emitter voltage with an upper limit reference voltage and a lower limit reference voltage; wherein the failure detector comprises: a second bipolar junction transistor in which a base terminal and a collector terminal are grounded; a current source configured to generate a bias current; a first resistor coupled between the current source and an emitter terminal of the second bipolar junction transistor to generate the upper limit reference voltage; a second resistor and a third resistor configured to divide a second base-emitter voltage of the second bipolar junction transistor to generate the lower limit reference voltage; a first comparator configured to compare the first base-emitter voltage with the upper limit reference voltage and configured to generate a first failure signal; and a second comparator configured to compare the first base-emitter voltage with the lower limit reference voltage and configured to generate a second failure signal. Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 9 – 21 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding Claim 9 , the prior art of record does not teach claimed limitation: “a second resistor and a third resistor configured to divide a second base-emitter voltage formed at the emitter of the second bipolar junction transistor to generate a lower limit reference voltage; a first comparator configured to compare the first base-emitter voltage with the upper limit reference voltage to generate a first failure signal; and a second comparator configured to compare the first base-emitter voltage with the lower limit reference voltage to generate a second failure signal” in combination with all other claimed limitations of claim 9 . Regarding Claims 10 – 16 , the claims are allowed as they further limit allowed claim 9. Regarding Claim 17 , the prior art of record does not teach claimed limitation: “generating an upper limit reference voltage and a lower limit reference voltage from the first base-emitter voltage, respectively; and comparing the temperature complementary voltage with the upper limit reference voltage or the lower limit reference voltage using a comparator to generate an error signal” in combination with all other claimed limitations of claim 17 . Regarding Claims 18 – 21 , the claims are allowed as they further limit allowed claim 17. Comments The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claim(s) 2. Therefore, no prior art rejection for claim(s) 2 – 8 is presented in this action. However, Claim(s) 1 is/are provisionally rejected on the ground of nonstatutory double patenting. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Trainer et al. (US 2024/0280420 A1) disclose a method of calibrating an electrical power system, the electrical power system comprising: a power electronics converter configured to convert between first and second voltage supplies, the converter comprising a plurality of semiconductor switches, each semiconductor switch comprising a transistor; a controller configured to provide switching signals to each of the semiconductor switches; a current sensor arranged to measure current through the converter to one of the first and second voltage supplies; a temperature sensor arranged to measure a temperature of one or more of the semiconductor switches; and a junction temperature measurement module configured to receive a current signal from the current sensor and a temperature signal from the temperature sensor, the method comprising: the controller providing a gate switching signal to the transistor (see claim 1). Tomioka et al. (US 12,625,012 B2) teach a temperature sensor device, comprising: a temperature sensor circuit; and a temperature sensor, wherein the temperature sensor comprises a PN junction element, configured to be a temperature sensing element, a variable current source, configured to supply different forward currents of at least two values to the PN junction element, and a constant voltage source, configured to output a constant voltage having the same temperature properties as a forward voltage of the PN junction element, wherein the temperature properties comprise a rate of change of voltage with temperature (see claim 1). Tulane et al. (US 2022/0018720 A1) suggest a temperature estimation method for estimating a junction temperature of a power transistor used in an electric vehicle inverter, the method comprising: measuring a temperature-dependent characteristic of a power semiconductor comprising the power transistor used in a power semiconductor module adapted for use in the electric vehicle inverter; and estimating, using a processor, the junction temperature of the power semiconductor using a transfer function (see claim 1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to GIOVANNI ASTACIO-OQUENDO whose telephone number is (571)270-5724. The examiner can normally be reached Monday - Friday, 8:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571-272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GIOVANNI ASTACIO-OQUENDO/Primary Examiner, Art Unit 2858 6/13/2026 Application/Control Number: 18/958,291 Page 2 Art Unit: 2858 Application/Control Number: 18/958,291 Page 3 Art Unit: 2858 Application/Control Number: 18/958,291 Page 4 Art Unit: 2858 Application/Control Number: 18/958,291 Page 5 Art Unit: 2858 Application/Control Number: 18/958,291 Page 6 Art Unit: 2858 Application/Control Number: 18/958,291 Page 7 Art Unit: 2858 Application/Control Number: 18/958,291 Page 8 Art Unit: 2858
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