DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant's arguments filed 8/4/2026 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed features because Elmer’s operand-zero indicators are not metadata identifying outputs or processing channels to be masked independent of input sparsity; applicant's arguments have fully been considered, but are not found to be persuasive.
Please note that the features upon which applicant relies (i.e., metadata identifying outputs, processing channels to be masked independent of input sparsity) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, Elmer’s zero data element indicator/zero weight indicator is independent from Elmer’s input data element/weight.
In response to applicant’s arguments with regard to the independent claim 10 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed features because Elmer’s zero data and zero weight indicators are not generated according to a determined output sparsity pattern and are not used to select matrix elements via output sparsity metadata; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, Elmer does teach/suggest the above claimed features as Elmer’s zero data element/zero weight is part of the pattern of data being processed by systolic array, and zero data element and zero weight indicators are generated according to the pattern of data having zero data element and zero weight, and the zero data element and zero weight indicators are used to select whether corresponding element in the systolic array carry out or skips its processing.
As applicant appears to be applying the above arguments for independent claim 10 towards dependent claim 11, the examiner will also apply the above response for independent claim 10 towards dependent claim 11.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, one of ordinary skill in this art would be motivate to combine Elmer’s skipping operations into Menick’s device for the benefit of reducing power consumption (Elmer, col. 27, ll. 37-56).
.
In response to applicant’s arguments with regard to the dependent claims 7-9 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed features because Elmer does not disclose propagation of output sparsity metadata that masks output or channels independent of input sparsity; applicant's arguments have fully been considered, but are not found to be persuasive.
Please note that the features upon which applicant relies (i.e., propagation of output sparsity metadata that masks output, channels independent of input sparsity) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
I. TERMINAL DISCLAIMER
The terminal disclaimer filed on 8/4/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 12,190,158 has been reviewed and is accepted. The terminal disclaimer has been recorded.
II. ALLOWABLE SUBJECT MATTER
Claims 14-20 allowed.
Claims 2-4, and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
III. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Menick et al. (US Pub.: 2021/0256375) in view of Elmer (US Patent 11,842,169).
As per claim 1, Menick teaches/suggests an accelerator device comprising: a memory interconnect ([0103]); and a general-purpose processing engine coupled with the memory interconnect, the general-purpose processing engine having a matrix accelerator (Fig. 6; [0011]-[0012]; [0095]-[0096]; [0103]) configured to: operate with input matrix elements; and perform processing operations on the input matrix elements ([0027]; [0083]) (Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; and [0095]-[0104]).
Menick does not teach the accelerator device comprising:
parallel processing, the parallel processing configured to:
receive output sparsity metadata at a first pipeline stage, the output sparsity metadata associated with multiple processing channels, wherein the output sparsity metadata is independent of input sparsity of input; and
operating based on the output sparsity metadata, including configuring a first processing element associated with a first processing channel to bypass multiplication at a first processing element associated with a first processing channel.
Elmer teaches/suggests a device comprising: parallel processing (col. 6, ll. 18-38), the parallel processing configured to: receive output sparsity metadata (e.g. associated with zero data element indicator, zero weight indicator: Fig. 3-4; col. 3, ll. 25-37; col. 16, l.52 to col. 16, l. 43) at a first pipeline stage, the output sparsity metadata associated with multiple processing channels , wherein the output sparsity metadata is independent of input sparsity of input; and operating based on the output sparsity metadata, including configuring a first processing element associated with a first processing channel to bypass multiplication at a first processing element (e.g. associated with skipping multiplication operation: col. 3, ll. 25-37) associated with a first processing channel (Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; and col. 10, l. 46 to col. 19, l. 40).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Elmer’s skipping operations into Menick’s device for the benefit of reducing power consumption (Elmer, col. 27, ll. 37-56) to obtain the invention as specified in claim 1.
As per claim 5, Menick and Elmer teach/suggest all the claimed features of claim 1 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein each of the multiple processing elements includes a first source input associated with an accumulator value, a second source input associated with a first matrix, and a third source input associated with a second matrix (Menick, Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer, Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40).
As per claim 6, Menick and Elmer teach/suggest all the claimed features of claim 5 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein to bypass multiplication at the first processing element includes to output the accumulator value received at the first source input (Menick, Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer, Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40).
As per claim 7, Menick and Elmer teach/suggest all the claimed features of claim 6 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein to perform the processing operations includes to propagate the output sparsity metadata received at the first pipeline stage to a second pipeline stage and process input elements of the multiple processing channels according to the output sparsity metadata (Menick, Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer, Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40).
As per claim 8, Menick and Elmer teach/suggest all the claimed features of claim 7 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein the output sparsity metadata includes a bit associated with each of the multiple processing channels and a bit associated with each of multiple rows of an input matrix (Menick, Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer, Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40).
As per claim 9, Menick and Elmer teach/suggest all the claimed features of claim 8 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein, in a first processing cycle, the output sparsity metadata is to indicate to the first processing element to multiply input elements of a second matrix with input elements of a first matrix and, in a second processing cycle, to bypass multiplication operations for the input elements (Menick, Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer, Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40).
As per claim 10, Menick teaches/suggests a method comprising: having pattern to apply during training of a neural network (e.g. associated with sparsity pattern: [0057]); operating the neural network according to a determined sparsity pattern; performing multiply-accumulate operations to generate output sparsity based on matrix elements; and generating weight updates for a neural network according to multiply-accumulate operations, the weight updates having the output sparsity pattern (Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0060]-[0062]; [0083]; and [0095]-[0104]).
Menick does not teach the method comprising:
determining an output sparsity;
generating output sparsity metadata to process weights of the neural network, wherein the output sparsity metadata indicates operations to perform and operations to bypass;
being selected via the output sparsity metadata; and
being indicated by the output sparsity metadata.
Elmer teaches/suggests a device comprising: determining an output sparsity; generating output sparsity metadata (e.g. associated with zero data element indicator, zero weight indicator: Fig. 3-4; col. 3, ll. 25-37; col. 16, l.52 to col. 16, l. 43) to process weights of the neural network, wherein the output sparsity metadata indicates operations to perform and operations to bypass (e.g. associated with skipping multiplication operation: col. 3, ll. 25-37); being selected via the output sparsity metadata; and being indicated by the output sparsity metadata (Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; and col. 10, l. 46 to col. 19, l. 40).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Elmer’s skipping operations into Menick’s method for the benefit of reducing power consumption (Elmer, col. 27, ll. 37-56) to obtain the invention as specified in claim 10.
As per claim 11, Menick and Elmer teach/suggest all the claimed features of claim 10 above, where Menick and Elmer further teach/suggest the method comprising wherein performing multiply-accumulate operations to generate output sparsity includes: performing multiply-accumulate operations on matrix elements associated with a first channel; and bypassing the multiply-accumulate operations on the matrix elements associated with a second channel (Menick, Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer, Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40).
IV. PERTINENT RELATED PRIOR ART
Huang et al. (US Patent 10,817,260): discloses skipping multiplication operations with zeros in processing elements of the systolic array to reduce dynamic power consumption. A value of zero can be detected on an input data element entering each row of the array and respective zero indicators may be generated. These respective zero indicators may be passed to all the processing elements in the respective rows. The multiplication operation with the zero value can be skipped in each processing element based on the zero indicators, thus reducing dynamic power consumption
V. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 September 22, 2026
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