CTNF 18/958,384 CTNF 81273 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. I. DOUBLE PATENTING 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim 14 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,190,158 . Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the system described in claim 14 of the instant application (18/958,384) are taught in claim 14 of the patented application (US Patent 12,190,158), (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection) II. ALLOWABLE SUBJECT MATTER 12-151-07 AIA 07-97 12-51-07 Claim s 14--20 allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 2-4, and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. III. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, and 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Menick et al. (US Pub.: 2021/0256375) in view of Elmer (US Patent 11,842,169) . As per claim 1, Menick teaches/suggests an accelerator device comprising: a memory interconnect ([0103]); and a general-purpose processing engine coupled with the memory interconnect, the general-purpose processing engine having a matrix accelerator (Fig. 6; [0011]-[0012]; [0095]-[0096]; [0103]) configured to: operate with input matrix elements; and perform processing operations on the input matrix elements ([0027]; [0083]) (Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; and [0095]-[0104]). Menick does not teach the accelerator device comprising: parallel processing, the parallel processing configured to: receive output sparsity metadata at a first pipeline stage, the output sparsity metadata associated with multiple processing channels, wherein the output sparsity metadata is independent of input sparsity of input; and operating based on the output sparsity metadata, including configuring a first processing element associated with a first processing channel to bypass multiplication at a first processing element associated with a first processing channel. Elmer teaches/suggests a device comprising: parallel processing (col. 6, ll. 18-38), the parallel processing configured to: receive output sparsity metadata (e.g. associated with zero data element indicator, zero weight indicator: Fig. 3-4; col. 3, ll. 25-37; col. 16, l.52 to col. 16, l. 43) at a first pipeline stage, the output sparsity metadata associated with multiple processing channels , wherein the output sparsity metadata is independent of input sparsity of input; and operating based on the output sparsity metadata, including configuring a first processing element associated with a first processing channel to bypass multiplication at a first processing element (e.g. associated with skipping multiplication operation: col. 3, ll. 25-37) associated with a first processing channel (Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; and col. 10, l. 46 to col. 19, l. 40). It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Elmer ’s skipping operations into Menick ’s device for the benefit of reducing power consumption ( Elmer , col. 27, ll. 37-56) to obtain the invention as specified in claim 1. As per claim 5, Menick and Elmer teach/suggest all the claimed features of claim 1 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein each of the multiple processing elements includes a first source input associated with an accumulator value, a second source input associated with a first matrix, and a third source input associated with a second matrix ( Menick , Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer , Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40). As per claim 6, Menick and Elmer teach/suggest all the claimed features of claim 5 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein to bypass multiplication at the first processing element includes to output the accumulator value received at the first source input ( Menick , Fig. 6; [0011]- [0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer , Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40). As per claim 7, Menick and Elmer teach/suggest all the claimed features of claim 6 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein to perform the processing operations includes to propagate the output sparsity metadata received at the first pipeline stage to a second pipeline stage and process input elements of the multiple processing channels according to the output sparsity metadata ( Menick , Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer , Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40). As per claim 8, Menick and Elmer teach/suggest all the claimed features of claim 7 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein the output sparsity metadata includes a bit associated with each of the multiple processing channels and a bit associated with each of multiple rows of an input matrix ( Menick , Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer , Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40). As per claim 9, Menick and Elmer teach/suggest all the claimed features of claim 8 above, where Menick and Elmer further teach/suggest the accelerator device comprising wherein, in a first processing cycle, the output sparsity metadata is to indicate to the first processing element to multiply input elements of a second matrix with input elements of a first matrix and, in a second processing cycle, to bypass multiplication operations for the input elements ( Menick , Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer , Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40). As per claim 10, Menick teaches/suggests a method comprising: having pattern to apply during training of a neural network (e.g. associated with sparsity pattern: [0057]); operating the neural network according to a determined sparsity pattern; performing multiply-accumulate operations to generate output sparsity based on matrix elements; and generating weight updates for neural network according to multiply-accumulate operations, the weight updates having the output sparsity pattern (Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0060]-[0062]; [0083]; and [0095]-[0104]). Menick does not teach the method comprising: determining an output sparsity; generating output sparsity metadata to process weights of the neural network, wherein the output sparsity metadata indicates operations to perform and operations to bypass; being selected via the output sparsity metadata; and being indicated by the output sparsity metadata. Elmer teaches/suggests a device comprising: determining an output sparsity; generating output sparsity metadata (e.g. associated with zero data element indicator, zero weight indicator: Fig. 3-4; col. 3, ll. 25-37; col. 16, l.52 to col. 16, l. 43) to process weights of the neural network, wherein the output sparsity metadata indicates operations to perform and operations to bypass (e.g. associated with skipping multiplication operation: col. 3, ll. 25-37); being selected via the output sparsity metadata; and being indicated by the output sparsity metadata (Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; and col. 10, l. 46 to col. 19, l. 40). It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Elmer ’s skipping operations into Menick ’s method for the benefit of reducing power consumption ( Elmer , col. 27, ll. 37-56) to obtain the invention as specified in claim 10. As per claim 11, Menick and Elmer teach/suggest all the claimed features of claim 10 above, where Menick and Elmer further teach/suggest the method comprising wherein performing multiply-accumulate operations to generate output sparsity includes: performing multiply-accumulate operations on matrix elements associated with a first channel; and bypassing the multiply-accumulate operations on the matrix elements associated with a second channel ( Menick , Fig. 6; [0011]-[0012]; [0021]-[0027]; [0057]; [0083]; [0095]-[0104]; and Elmer , Fig. 1-4; col. 2, l. 13 to col. 6, l. 38; col. 10, l. 46 to col. 19, l. 40). IV. CLOSING COMMENTS CONCLUSION STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday. IMPORTANT NOTE If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHUN KUAN LEE/Primary Examiner Art Unit 2181 May 13, 2026 Application/Control Number: 18/958,384 Page 2 Art Unit: 2181 Application/Control Number: 18/958,384 Page 3 Art Unit: 2181 Application/Control Number: 18/958,384 Page 4 Art Unit: 2181 Application/Control Number: 18/958,384 Page 5 Art Unit: 2181 Application/Control Number: 18/958,384 Page 6 Art Unit: 2181 Application/Control Number: 18/958,384 Page 7 Art Unit: 2181 Application/Control Number: 18/958,384 Page 8 Art Unit: 2181 Application/Control Number: 18/958,384 Page 9 Art Unit: 2181 Application/Control Number: 18/958,384 Page 10 Art Unit: 2181 Application/Control Number: 18/958,384 Page 11 Art Unit: 2181
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