DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a 2nd NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 05/15/2026. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 18958550 filed 11/25/2024 is a Continuation of 17233097, filed 04/16/2021, now U.S. Patent No.12,158,814 which is a Continuation in Part of 16370645, filed 03/29/2019, now U.S. Patent No.10,983,866 which is a Continuation of 15418333, filed 01/27/2017, now U.S. Patent No. 10,268,548 which is a Continuation of 14454516, filed 08/07/2014, now U.S. Patent No.9,558,069.
Response to Arguments
Applicant’s arguments, see Amendment/ Remarks filed 05/15/2026, with respect to the rejection of Claims1-20 under 35 U.S.C. 102(a)(1) as being anticipated by KIM (Pub. No. US 20130107633), have been fully considered and are persuasive.
Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of JOO et al. (Pub. No. US 20130117634) Pub. Date: 2013-05-09.
During an interview on April 29, 2026, with Applicant’s representative Michael Gencarella, the Claims rejection was discussed in view of the KIM (Pub. No. US 20130107633) reference, especially with respect to storing the results on the erase block "as metadata". The Examiner indicated that the Claims should be amended accordingly to more clearly define the metadata. No agreement was reached as to the prior art rejection, pending further search and Examination.
The Examiner agrees with Applicant’s arguments that KIM fails to disclose a Storage System Controller External to the Solid-State Storage Device, Storing Results of a Tuning Process as Metadata Associated with an Erase Block, and Selecting a Tuning Processes Based on Metadata.
JOO, under a new ground(s) of rejection, discloses the above limitations, as set forth in the present office action below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JOO et al. (Pub. No. US 20130117634).
Regarding independent Claims 1, 8 and 15, JOO discloses a memory system comprising a nonvolatile memory device, and methods, comprising:
providing, by a processor of a storage system controller, where the controller, is external to a solid-state storage device, [0065] Referring to FIG. 2, data storage system 3000 comprises a multi-bit memory device 3100 as a non-volatile memory device, a memory controller 3200, and a host 3300. Multi-bit memory device 3100 can be formed of one or more memory chips, where the memory controller3200 is separated and external to the memory device 3100.
a first tuning process to be performed on an erase block of the solid-state storage device; [0124] FIG. 10 describing a main program operation of a memory system. [0126] In operation S500, “first tuning process” data is read from a selected page of first memory region 3101 via page buffer 3103. In operation S520, data read from first memory region 3101 is sent to memory controller 3200, and memory controller 3200 performs an error detecting and correcting operation on the transferred data.
storing results of the first tuning process on the erase block as metadata in the solid-state storage device; [0127] In operation S530, “storing results” memory controller 3200 determines whether an error correction operation is passed. If so (S530=Pass), the method proceeds to operation S560. Otherwise (S530=Fail), the method proceeds to operation S540. In operation S540, corrected data is transferred to multi-bit memory device 3100. In operation S550, setup of the transferred data is performed within page buffer 3103 for programming of main region 3102.
with respect to “storing results as metadata” [0073] FIGS. 3A to 3D. First and second memory regions 3101 and 3102 constitute a memory cell array of multi-bit memory device 3100. Although not illustrated in drawings, the memory cell array may further comprise other regions, such as a metadata region, a reserved region, and the like. These regions are typically defined by logical divisions rather than physical divisions.
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata.
[0128] In operation S560, “second tuning process” an SLC data recover read operation is performed. [0129] In operation S570, data read from first memory region 3101 via the SLC data recover read operation is sent to memory controller 3200, and memory controller 3200 performs an error detecting and correcting operation on the transferred data. In operation S580, memory controller 3200 determines whether an error correction operation is passed. Where the error correction operation is a failure (S580=Fail), the method proceeds to operation S590.
Regarding Claims 2, 9, 16, JOO discloses wherein the first tuning process comprises a first number of read voltages, and the second tuning comprises a second larger number of read voltages. [0126] In operation S500, “first number of read voltages” data is read from a selected page of first memory region 3101 via page buffer 3103. [0128] In operation S560, “second larger number of read voltages” an SLC data recover read operation is performed. In the SLC data recover read operation, a read operation is performed two times with respect to a threshold voltage distribution (or, a data state) (including a coupled distribution and an uncoupled distribution) using a first read voltage and a second read voltage to reduce a read error generated due to the wordline coupling.
Regarding Claims 3, 10, 17, JOO discloses wherein the first tuning process comprises a first number of read voltages, and the second tuning process comprises a first number of write voltages. 0125] As described above, a main program operation starts under the control of memory controller 3200 when data of the minimum program unit is gathered in first memory region 3101. The main program operation may include two or more SLC read operations and a reprogram operation. For simplicity of description, a procedure associated with one SLC read operation is illustrated in FIG. 10.
Regarding Claims 4, 11, 18, JOO discloses wherein the first tuning process comprises a first number of read voltages , and the second tuning process comprises a first number of programming duration times. [0057] In some embodiments, the first programming is performed in an Incremental Step Pulse Programming (ISPP) method in which a program voltage is increased by an increment in successive program loops. Moreover, in some embodiments, the first programming comprises a verification operation. In the verification operation, at least one program state may be verified.
Regarding Claims 5, 12, 19, JOO discloses wherein the first tuning process is different than the second tuning process. [0126] In operation S500, “first tuning process” data is read from a selected page of first memory region 3101 via page buffer 3103. [0128] In operation S560, “second tuning process” an SLC data recover read operation is performed.
Regarding Claims 6, 7, 13, 14, 20, JOO discloses wherein the solid-state storage device is a managed flash storage device that offloads management responsibilities to the storage system controller; and converting the erase block from multilevel cell (MLC) operation to single level cell (SLC) operation. [0065] Referring to FIG. 2, As a data storage device or a memory system, multi-bit memory device 3100 and memory controller 3200 may constitute a memory card, a Solid State Drive (SSD), a memory stick, or the like. Multi-bit memory device 3100 comprises a plurality of memory blocks (or, sectors/banks) each having memory cells arranged in rows and columns. Each of the memory cells stores multi-bit (or, multi-level) data.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,158,814. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,158,814, and thus anticipate the Claims of the instant Application, (See, TABLE A). Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
TABLE A: DP Claims comparison
18958550 Instant Application
(U.S. Patent No. 12,158,814)
1. A method, comprising:
providing, by a processor of a storage system controller that is external to a solid-state storage device,
a first tuning process to be performed on an erase block of the solid-state storage device;
storing results of the first tuning process on the erase block as metadata in the solid-state storage device; and
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata.
1. A method, comprising:
providing, by a processor of a storage controller of a storage system that is external to a solid-state storage device,
a first tuning process, having a first set of tuning options, to be performed on an erase block of solid-state storage memory of the solid-state storage device;
identifying one or more pages of the erase block that fail readability after the first tuning process on the erase block is completed; and
providing a second tuning process, having a differing second set of tuning options, to be performed on the one or more pages that failed readability while avoiding performing the first tuning process on the erase block.
8. A non-transitory computer readable storage medium storing instructions which, when executed, cause a processor of a storage system controller to:
provide, by the storage system controller that is external to a solid-state storage device, a first tuning process to be performed on an erase block of the solid-state storage device;
store results of the first tuning process on the erase block as metadata in the solid-state storage device; and
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata.
9. A non-transitory computer readable storage medium storing instructions which, when executed, cause a processor to:
provide, by the processor that is external to a solid-state storage device, a first tuning process, having a first set of tuning options, to be performed on an erase block of solid-state storage memory of the solid-state storage device;
identify one or more pages of the erase block that fail readability after the tuning with the first tuning process on the erase block has completed; and
provide a second tuning process, having a differing second set of tuning options, to be performed on the one or more pages that failed readability while avoiding performing the first tuning process on the erase block.
15. A system, comprising:
a solid-state storage device; and a storage system controller comprising processor, operatively coupled and external to the solid-state storage device, configured to:
provide a first tuning process to be performed on an erase block of the solid-state storage device;
store results of the first tuning process on the erase block as metadata in the solid-state storage device; and
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata.
14. A system, comprising:
a solid-state storage device comprising solid-state storage memory; and a processing device, operatively coupled and external to the solid-state storage device, configured to:
provide a first tuning process, having a first set of tuning options, to be performed on an erase block of the solid-state storage memory of the solid-state storage device;
identify one or more pages of the erase block that fail readability after the first tuning process on the erase block is completed; and
provide a second tuning process, having a differing second set of tuning options, to be performed on the one or more pages that failed readability while avoiding performing the first tuning process on the erase block.
2, 9, 16. The method of claim 1, wherein the first tuning process comprises a first number of read voltages with which to tune reading the erase block, and the second tuning comprises a second, larger number of read voltages with which to tune the reading the erase block.
2, 10, 15. The method of claim 1, wherein the first set of tuning options comprises a first number of read voltages with which to tune reading the solid-state storage memory, and the second set of tuning options comprises a second, larger number of read voltages with which to tune the reading the solid-state storage memory.
3, 10, 17. The method of claim 1, wherein the first tuning process comprises a first number of read voltages with which to tune reading the erase block, and the second tuning process comprises a first number of write voltages with which to tune programming the erase block.
3, 11, 16. The method of claim 1, wherein the first set of tuning options comprises a first number of read voltages with which to tune reading the solid-state storage memory, and the second set of tuning options comprises a first number of write voltages with which to tune programming the solid-state storage memory.
4, 11, 18. The method of claim 1, wherein the first tuning process comprises a first number of read voltages with which to tune reading the erase block, and the second tuning process comprises a first number of programming duration times with which to tune programming the erase block.
4, 12, 17. The method of claim 1, wherein the first set of tuning options comprises a first number of read voltages with which to tune reading the solid-state storage memory, and the second set of tuning options comprises a first number of programming duration times with which to tune programming the solid-state storage memory.
5, 12, 19. The method of claim 1, wherein the first tuning process is different than the second tuning process.
1, 9, 14. provide a second tuning process, having a differing second set of tuning options,
7, 14. The method of claim 1, further comprising: converting the erase block from multilevel cell (MLC) operation to single level cell (SLC) operation based on a subsequent result of the second tuning process.
6, 13, 19. The method of claim 1, further comprising: converting the one or more pages of the solid-state storage memory from multilevel cell (MLC) operation to single level cell (SLC) operation, based on a result of the performing the second tuning process or a repetition thereof.
6, 13, 20. The method of claim 1, wherein the solid-state storage device is a managed flash storage device that offloads management responsibilities to the storage system controller.
7. The method of claim 1, wherein the storage system comprises a heterogeneous mix of solid-state storage devices having at least two differing erase block sizes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: May 27, 2026
Non-Final Rejection 20260526
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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