DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 11/25/2024. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 18958550 filed 11/25/2024 is a Continuation of 17233097, filed 04/16/2021, now U.S. Patent No.12,158,814 which is a Continuation in Part of 16370645, filed 03/29/2019, now U.S. Patent No.10,983,866 which is a Continuation of 15418333, filed 01/27/2017, now U.S. Patent No. 10,268,548 which is a Continuation of 14454516, filed 08/07/2014, now U.S. Patent No.9,558,069.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/25/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM (Pub. No. US 20130107633) Pub. Date: 2013-05-02.
Regarding independent Claims 1, 8 and 15, KIM discloses a reading method of a nonvolatile memory device, comprising:
providing, by a processor of a storage system controller that is external to a solid-state storage device, [0061] Referring to FIG. 10, the data processing system 1000 can be configured to include a data storage device 1100 and a host device 1500. The data storage device 1100 can be configured as a solid state drive (hereinafter, referred to as an `SSD`).
a first tuning process to be performed on an erase block of the solid-state storage device; [0039] FIG. 3 illustrates a reading method of a nonvolatile memory device according. FIG. 4 illustrates a part of a memory cell array of the nonvolatile memory device, “an erase block” illustrating the reading method. [0040] First, at step S110, “first tuning process” a read operation of a selected memory cell MC1 is performed. For example, any one of selection read voltages Vrd0, Vrd1 and Vrd2 is applied to the selected memory cell MC1, and a non-selection read voltage Vpass_s is applied to non-selected memory cells MC0 and MC2 to MCm. The read operation of the selected memory cell MC1 is performed under such a bias condition.
storing results of the first tuning process on the erase block as metadata in the solid-state storage device; [0041] At step S120, it is decided whether or not the read operation of the selected memory cell MC1 succeeds. On the other hand, when the read operation of the selected memory cell MC1 has not succeeded (i.e., the read operation fails), the procedure proceeds to step S130.
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata. [0042] At step S130, a read retry operation of the selected memory cell MC1 is performed “second tuning process”. In the read retry operation, a non-selection read voltage having a level different from that of the non-selection read voltage Vpass_s applied in the read operation at the step S110 is applied to the non-selected memory cells MC0 and MC2 to MCm. For example, a non-selection read voltage decreased by a predetermined voltage variation (.DELTA.V) from the non-selection read voltage Vpass_s applied in the read operation at the step S110, i.e., a variable non-selection read voltage Variable Vpass, is applied to the non-selected memory cells MC0 and MC2 to MCm.
Regarding Claims 2, 9, 16, KIM discloses wherein the first tuning process comprises a first number of read voltages, and the second tuning comprises a second larger number of read voltages. [0036] FIG. 2. The memory cell is programmed in any one of an erase state E and a plurality of program states P0, P1 and P2. In the read operation, any one of selection read voltages Vrd0, Vrd1 and Vrd2 is applied to the selected word line. The first selection read voltage Vrd0 corresponds to a voltage between the erase state E and the first program state P0.
Regarding Claims 3, 10, 17, KIM discloses wherein the first tuning process comprises a first number of read voltages, and the second tuning process comprises a first number of write voltages. [0028] The SLC is programmed to have a threshold voltage corresponding to any one of an erase state and a program state. As another example, each of the memory cells of a multi-level cell (MLC) can store 2 or more-bit data. The MLC is programmed to have a threshold voltage corresponding to any one of an erase state and a plurality of program states.
Regarding Claims 4, 11, 18, KIM discloses wherein the first tuning process comprises a first number of read voltages , and the second tuning process comprises a first number of programming duration times. [0047] At the step S150, it is determined whether the read retry operation has been performed a predetermined number of times (maximum L times). When the read operation has been repeated the predetermined number of times and the read operation has not succeeded, the procedure proceeds to step S160. That is, the read operation has failed and the procedure is finished.
Regarding Claims 5, 12, 19, KIM discloses wherein the first tuning process is different than the second tuning process. [0042] At step S130, For example, a non-selection read voltage decreased by a predetermined voltage variation (.DELTA.V) from the non-selection read voltage Vpass_s applied in the read operation at the step S110, i.e., a variable non-selection read voltage Variable Vpass, is applied to the non-selected memory cells MC0 and MC2 to MCm.
Regarding Claims 6, 7, 13, 14, 20, KIM discloses wherein the solid-state storage device is a managed flash storage device that offloads management responsibilities to the storage system controller; and converting the erase block from multilevel cell (MLC) operation to single level cell (SLC) operation. [0028] FIG. 1 The memory cell array 110 includes a plurality of memory cells arranged in intersection portions of bit lines BL0 to BLn and word lines WL0 to WLn. As an example, each of the memory cells can store 1-bit data. The memory cell is referred to as a single level cell (SLC). The SLC is programmed to have a threshold voltage corresponding to any one of an erase state and a program state. As another example, each of the memory cells of a multi-level cell (MLC) can store 2 or more-bit data.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12,158,814. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,158,814, and thus anticipate the Claims of the instant Application, (See, TABLE A). Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
TABLE A: DP Claims comparison
18958550 Instant Application
(U.S. Patent No. 12,158,814)
1. A method, comprising:
providing, by a processor of a storage system controller that is external to a solid-state storage device,
a first tuning process to be performed on an erase block of the solid-state storage device;
storing results of the first tuning process on the erase block as metadata in the solid-state storage device; and
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata.
1. A method, comprising:
providing, by a processor of a storage controller of a storage system that is external to a solid-state storage device,
a first tuning process, having a first set of tuning options, to be performed on an erase block of solid-state storage memory of the solid-state storage device;
identifying one or more pages of the erase block that fail readability after the first tuning process on the erase block is completed; and
providing a second tuning process, having a differing second set of tuning options, to be performed on the one or more pages that failed readability while avoiding performing the first tuning process on the erase block.
8. A non-transitory computer readable storage medium storing instructions which, when executed, cause a processor of a storage system controller to:
provide, by the storage system controller that is external to a solid-state storage device, a first tuning process to be performed on an erase block of the solid-state storage device;
store results of the first tuning process on the erase block as metadata in the solid-state storage device; and
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata.
9. A non-transitory computer readable storage medium storing instructions which, when executed, cause a processor to:
provide, by the processor that is external to a solid-state storage device, a first tuning process, having a first set of tuning options, to be performed on an erase block of solid-state storage memory of the solid-state storage device;
identify one or more pages of the erase block that fail readability after the tuning with the first tuning process on the erase block has completed; and
provide a second tuning process, having a differing second set of tuning options, to be performed on the one or more pages that failed readability while avoiding performing the first tuning process on the erase block.
15. A system, comprising:
a solid-state storage device; and a storage system controller comprising processor, operatively coupled and external to the solid-state storage device, configured to:
provide a first tuning process to be performed on an erase block of the solid-state storage device;
store results of the first tuning process on the erase block as metadata in the solid-state storage device; and
selecting a second tuning process to be performed on the erase block based on accessing the results of the tuning process in the metadata.
14. A system, comprising:
a solid-state storage device comprising solid-state storage memory; and a processing device, operatively coupled and external to the solid-state storage device, configured to:
provide a first tuning process, having a first set of tuning options, to be performed on an erase block of the solid-state storage memory of the solid-state storage device;
identify one or more pages of the erase block that fail readability after the first tuning process on the erase block is completed; and
provide a second tuning process, having a differing second set of tuning options, to be performed on the one or more pages that failed readability while avoiding performing the first tuning process on the erase block.
2, 9, 16. The method of claim 1, wherein the first tuning process comprises a first number of read voltages with which to tune reading the erase block, and the second tuning comprises a second, larger number of read voltages with which to tune the reading the erase block.
2, 10, 15. The method of claim 1, wherein the first set of tuning options comprises a first number of read voltages with which to tune reading the solid-state storage memory, and the second set of tuning options comprises a second, larger number of read voltages with which to tune the reading the solid-state storage memory.
3, 10, 17. The method of claim 1, wherein the first tuning process comprises a first number of read voltages with which to tune reading the erase block, and the second tuning process comprises a first number of write voltages with which to tune programming the erase block.
3, 11, 16. The method of claim 1, wherein the first set of tuning options comprises a first number of read voltages with which to tune reading the solid-state storage memory, and the second set of tuning options comprises a first number of write voltages with which to tune programming the solid-state storage memory.
4, 11, 18. The method of claim 1, wherein the first tuning process comprises a first number of read voltages with which to tune reading the erase block, and the second tuning process comprises a first number of programming duration times with which to tune programming the erase block.
4, 12, 17. The method of claim 1, wherein the first set of tuning options comprises a first number of read voltages with which to tune reading the solid-state storage memory, and the second set of tuning options comprises a first number of programming duration times with which to tune programming the solid-state storage memory.
5, 12, 19. The method of claim 1, wherein the first tuning process is different than the second tuning process.
1, 9, 14. provide a second tuning process, having a differing second set of tuning options,
7, 14. The method of claim 1, further comprising: converting the erase block from multilevel cell (MLC) operation to single level cell (SLC) operation based on a subsequent result of the second tuning process.
6, 13, 19. The method of claim 1, further comprising: converting the one or more pages of the solid-state storage memory from multilevel cell (MLC) operation to single level cell (SLC) operation, based on a result of the performing the second tuning process or a repetition thereof.
6, 13, 20. The method of claim 1, wherein the solid-state storage device is a managed flash storage device that offloads management responsibilities to the storage system controller.
7. The method of claim 1, wherein the storage system comprises a heterogeneous mix of solid-state storage devices having at least two differing erase block sizes.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Cho et al. US 20120265927 [0019] wherein the controller includes a memory that receives and stores first data read from the nonvolatile memory using a first read voltage, second data read from the nonvolatile memory using a second read voltage, information on the first read voltage and information on the second read voltage, an error correction code (ECC) decoder that corrects an error bit using the first data and the second data, and a central processor unit (CPU) that compares the first read voltage and the second read voltage and determines to reprogram the nonvolatile memory according to the comparison result of the first read voltage and the second read voltage, when the error bit of the first data cannot be corrected and the error bit of the second data can be corrected.
Dodson et al. US 20140380095 See Abstract. Techniques for handling uncorrectable errors occurring during memory accesses reduce the likelihood of mis-correction of errors due to the presence of noise. In-flight memory requests are marked for retry, and responses to pending request are flushed. A calibration command may be issued after the predetermined time period has elapsed. After the predetermined time period has elapsed and any calibration performed, the requests marked for retry are issued to the memory device.
Kim et al. US 20140281770 Abstract. In a method of reading data from a nonvolatile memory device, a first read operation for memory cells coupled to a first word line is performed by applying a first read voltage to the first word line, a first read retry is performed to obtain an optimal read level regardless or independent of whether data read by the first read operation is error-correctable, and the optimal read level is stored to perform a subsequent second read operation using the optimal read level. Related methods and devices are also discussed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: February 20, 2026
Non-Final Rejection 20260213
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV