DETAILED ACTION
This office action is in response to the application filed on 11/25/2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawing
The drawing submitted on 11/25/2024 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/26/2026 and 05/28/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9-13, 18-20 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Ejury et al. (US Patent or PG Pub. No. 20150077081, hereinafter ‘081).
Claim 1, ‘081 teaches an apparatus (e.g., see Fig. 1-6) comprising: a bootstrap capacitor refresh pulse generation circuit (e.g., the circuits comprising 208) configured to generate a refresh pulse to turn on a low-side switch (e.g., M2) of a power converter once an off-time of the low-side switch exceeds a predetermined threshold (e, g., Vth_low, see Fig. 4-6); and a logic gate (e.g., the OR gate of 210, see Fig. 4) configured to receive the refresh pulse and a low-side pulse width modulation (PWM) signal (e.g., PWM_GL), and generate a drive signal (e.g., GL) applied to a gate of the low-side switch of the power converter (e.g., see Fig. 4-6).
Claim 2, ‘081 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the power converter is a buck converter (e.g., see p0017]) comprising: a high-side switch (e.g., M1) and the low-side switch connected in series between an input voltage bus (e.g., Vin) and ground (e.g., see Fig. 1-6); an inductor (e.g., 122) connected in series between a common node of the high-side switch and the low-side switch, and an output voltage bus (e.g., the DC bus of Vout); and an output capacitor (e.g., 106) connected between the output voltage bus and ground (e.g., see Fig. 1-6).
Claim 3, ‘081 teaches the limitations of claim 1 as discussed above. It further teaches that wherein: the logic gate is an OR gate (e.g., see Fig. 4); and the bootstrap capacitor refresh pulse generation circuit is a timer (e.g., 208, 114) configured to measure duration of time after the low-side switch is turned off (e.g., the time corresponding to the VBOOT drops below Vth_low, see [0026][0033][0038], Fig. 6), and generate the refresh pulse once the off-time of the low-side switch exceeds the predetermined threshold, and wherein: the low-side gate drive signal is fed into a first input of the OR gate (e.g., see Fig. 4- 6); an output of the timer (e.g., the output of 208) is fed into a second input of the OR gate (e.g., see Fig. 4- 6); and an output of the OR gate is applied to the gate of the low-side switch through a low-side driver (e.g., 120, see Fig. 4-6)).
Claim 4, ‘081 teaches the limitations of claim 1 as discussed above. It further teaches that wherein: the logic gate is an OR gate; and the bootstrap capacitor refresh pulse generation circuit is a counter (e.g., the counter, see [0033]) configured to count the number of clock cycles after the low-side switch is turned off (e.g., see Fig. 6), and generate the refresh pulse once the off-time of the low-side switch exceeds the predetermined threshold (e.g., when Vth_low drops below after LS being turned off, see Fig. 6), and wherein: the low-side gate drive signal is fed into a first input of the OR gate; an output of the counter is fed into a second input of the OR gate; and an output of the OR gate is applied to the gate of the low-side switch through a low-side driver (e.g., see [0033], Fig. 6).
Claim 18, ‘081 teaches a system (e.g., see Fig. 1-6) comprising: a power converter (e.g., 100, 250) connected between an input voltage bus (e.g., Vin) and an output voltage bus (e.g., Vout); and a controller (e.g., the controller) electrically coupled to the power converter, wherein the controller comprises a bootstrap capacitor refresh control apparatus, and wherein: the bootstrap capacitor refresh control apparatus is configured to measure an off-time of a low-side switch of the power converter (e.g., when Vth_low drops below after LS being turned off, see Fig. 6); and the bootstrap capacitor refresh control apparatus is configured to generate a refresh pulse to turn on the low-side switch of the power converter once the off-time of the low-side switch exceeds a predetermined threshold (e.g., the time corresponding to the VBOOT drops below Vth_low, see Fig. 6).
Claim 19, ‘081 teaches the limitations of claim 18 as discussed above. It further teaches that wherein the power converter comprises: a high-side switch (e.g., M1) and the low-side switch connected in series between the input voltage bus and ground; an inductor (e.g., 122) connected in series between a common node of the high-side switch and the low-side switch, and the output voltage bus; and an output capacitor (e.g., 106) connected between the output voltage bus and ground (e.g., see Fig. 1-6).
Claim 20, ‘081 teaches the limitations of claim 18 as discussed above. It further teaches that wherein: the bootstrap capacitor refresh control apparatus comprises an OR gate (e.g., see Fig. 4) and a timer (e.g., 208), and wherein: a low-side PWM signal is fed into a first input of the OR gate (e.g., see Fig. 4); an output of the timer is fed into a second input of the OR gate (e.g., see Fig. 4); and an output of the OR gate is applied to a gate of the low-side switch through a low-side driver (e.g., see Fig. 4).
For method claims 9-13, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Allowable Subject Matter
Claims 5-8, 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claim 5, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “wherein: the predetermined threshold is dynamically adjustable, and wherein the predetermined threshold is inversely related to a current flowing through the power converter”.
For claim 6, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “wherein: a width of the refresh pulse is dynamically adjustable, and wherein the width of the refresh pulse is inversely related to a slope of a current flowing through the power converter”.
For claim 7, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “wherein: a width of the refresh pulse is dynamically adjustable, and wherein the width of the refresh pulse is inversely related to a slope of a current flowing through the power converter”.
For claim 8, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “wherein: a width of the refresh pulse is dynamically adjustable, and wherein the width of the refresh pulse is inversely related to a comp voltage of the power converter”.
For claim 14, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “dynamically adjusting the predetermined threshold based on a current flowing through the power converter”.
For claim 15, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “dynamically adjusting a width of the refresh pulse based on a slope of a current flowing through the power converter”.
For claim 16, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “dynamically adjusting a width of the refresh pulse based on a comp signal of the power converter”.
For claim 17, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “determining a first width of the refresh pulse based on a slope of a current flowing through the power converter; and determining a second width of the refresh pulse based on a comp signal of the power converter, wherein a width of the refresh pulse is alternately set using the first width and the second width”.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JUE ZHANG/
Primary Examiner, Art Unit 2838
Prosecution Insights