DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 is objected to because of the following informality: on line 2 of claim 19, the number “180” needs to be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arai (U.S. Patent Publication No. 2019/0371715).
Regarding claim 1, in Figures 1A, 1B, and 2, Arai discloses a printed circuit board comprising: an insulating portion (21); a first pad (32) disposed on a bottom of the insulating portion; a first solder resist layer (33) disposed on the bottom of the insulating portion, covering at least a first portion of the first pad, and having a first opening (33X) overlapping at least a second portion of the first pad; a first barrier layer (34) disposed on the second portion of the first pad corresponding to the first opening; a first surface treatment layer (96) disposed on the first barrier layer; a second pad (60) disposed on a top of the insulating portion; a second solder resist layer (43) disposed on the top of the insulating portion, covering at least a third portion of the second pad, and having a second opening overlapping at least a fourth portion of the second pad; a metal post (70, Figures 1B) disposed on the second pad, and having at least a portion disposed in the second opening; and a second barrier layer (65) disposed between the second pad and the metal post.
Regarding claim 2, Arai discloses wherein the first barrier layer extends to a portion of an inner wall of the first opening (Figures 1A, 1B, and 2).
Regarding claim 3, Arai discloses wherein the first barrier layer is disposed along at least a portion of a side surface of the first surface treatment layer (Figures 1A, 1B, and 2).
Regarding claim 4, Arai discloses wherein the first surface treatment layer includes a first metal layer disposed on the barrier layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer (Figures 1A, 1B, and 2).
Regarding claim 5, Arai discloses a first seed layer disposed between the first barrier layer and the surface treatment layer (Figures 1A, 1B, and 2).
Regarding claim 6, Arai discloses wherein the first barrier layer extends to a portion of an inner wall of the first opening, and the first seed layer extends along the first barrier layer (Figures 1A, 1B, and 2).
Regarding claim 7, Arai discloses wherein the first barrier layer, the first seed layer, and the first surface treatment layer have substantially coplanar surfaces, respectively (Figures 1A, 1B, and 2).
Regarding claim 8, Arai discloses wherein one surface of the first surface treatment layer is a step from a lower surface of the first solder resist layer (Figures 1A, 1B, and 2).
Regarding claim 9, Arai discloses wherein the barrier layer includes a metal different from a metal of the first pad (paragraph [0045]; Figures 1A, 1B, and 2).
Regarding claim 10, Arai discloses wherein the second barrier layer is disposed on the second pad, and extends to portions of an inner wall of the second opening and an upper surface of the second solder resist (Figures 1A, 1B).
Regarding claim 11, Arai discloses a second seed layer disposed between the second barrier layer and the metal post, and extending along the second barrier layer.
Regarding claim 12, Arai discloses a second surface treatment layer disposed on the metal post (Figures 1A, 1B).
Regarding claim 13, Arai discloses wherein the second surface treatment layer, the second barrier layer, and the second seed layer have substantially coplanar surfaces, respectively (Figures 1A, 1B).
Regarding claim 14, Arai discloses wherein the second surface treatment layer includes a first metal layer disposed on the metal post, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer (Figures 1A, 1B).
Regarding claim 15, Arai discloses wherein the insulating portion includes a first insulating layer and a second insulating layer, and the printed circuit board further comprises a first wiring layer and a second wiring layer disposed on the first insulating layer and the second insulating layer, respectively, wherein the first wiring layer and the second wiring layer are connected to the first pad and the second pad (Figures 1A, 1B, and 2).
Regarding claim 16, in Figures 1A and 1B, Arai discloses a printed circuit board comprising: an insulating portion (41); a pad (60) disposed on a top of the insulating portion; a solder resist layer (43) disposed on the top of the insulating portion, covering at least a first portion of the pad (solder resist layer 43 covers side portions of layer 60), and having an opening (43X) overlapping at least a second portion (top portion of layer 60) of the pad; a barrier layer (65) in contact with the pad, and extending onto portions of an inner wall of the opening and an upper surface of the solder resist (Figure 1B); and a metal post (70) disposed on the barrier layer, wherein: the pad includes a first metal (Ni, Pd, Au, paragraph [0054]), and the barrier layer includes a material (copper, paragraph [0028]) different from the first metal of the pad.
Regarding claim 17, Arai discloses wherein the barrier layer is free of the first meta (paragraphs [0028], [0054]).
Regarding claim 18, Arai discloses wherein the material of the barrier layer includes at least one selected from titanium (Ti), aluminum (Al), tin (Sn), and lead (Pb) (paragraph [0028]).
Regarding claim 19, Arai discloses wherein the material of the barrier layer 180 includes a conductive carbon-based material (paragraph [0028]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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