DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeh et al. U.S. Patent Publication No. 2020/0064702 (hereinafter Yeh) in view of Choi et al. U.S. Patent Publication No. 9,853,096 (hereinafter Choi) and further view of Xu et al. U.S. Patent Publication No. 2018/0366495 (hereinafter Xu).
Consider claim 15, Yeh teaches an electronic device (Figure 1, element 10), comprising: a display device for providing an image (Figure 1, element 14), and wherein the display device comprises: a base part (Figure 9, element 26) comprising a display area comprising a plurality of each having at least one switching element and a light-emitting element (Figure 3, element 44 and TD), a non-display area surrounding the display area (Figure 4, IA1), and a through hole surrounded by the display area (Figure 10, element 52); a plurality of first lines extending in a first direction on the base part and connected to the plurality of pixels (Figure 10, first data line segments 102); connection lines bypassing the through hole and extending in the display area to connect between the first lines spaced apart from one another by the through hole among the plurality of first lines (Figure 10, supplement data lines 106). In addition, Yeh teaches supplemental data lines 106 may be formed from a layer of metal between passivation layer 72 and organic planarization layer 74 (as shown in FIG. 9) or another desired layer of metal in [0065] and figure 10.
Yeh does not appear to specifically disclose a first conductive layer comprising a first anode connection electrode connected to the at least one switching element; and a second conductive layer on the first conductive layer and comprising a second anode connection electrode connecting the first anode connection electrode with the light-emitting element, wherein the first lines and the first portion are in the second conductive layer, and the second portion is in the first conductive layer.
However, in a related field of endeavor, Choi teaches inactive area may be enclosed by the pixels in the active area (abstract) and further teaches a first conductive layer (Figure 9, 50-1) comprising a first anode connection electrode connected to the at least one switching element (Figure 9, elements 53-1 and 520); and a second conductive layer (Figure 9, 50-2) on the first conductive layer and comprising a second anode connection electrode connecting the first anode connection electrode with the light-emitting element (Figure 9, 53-2 and 42), wherein the first lines and the first portion are in the second conductive layer (Figure 9, plurality of D’), and the second portion is in the first conductive layer (Figure 9, D).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide two conductive layers as taught by Choi with the benefit that source-drain metal layer may be shorted to anode 42 of light-emitting diode 26 using a metal via structure. The metal via structure may be a metal via that includes lower via portion 53-1, which passes through a dielectric layer such as lower planarization layer 50-1, and that includes upper via portion 53-2, which passes through a dielectric layer such as upper planarization layer 50-2. Portions of the metal layer that form source-drain terminals 520 for transistor 28 may be used in forming data lines D on dielectric layer 540 under planarization layer 50-1. Portions of the metal layer that form via 53-1 may form supplemental data lines D' on planarization layer 50-1. Upper planarization layer 50-2 may overlap data lines D' and layer 50-1, SO that data lines D' are interposed between upper planarization layer 50-2 and lower planarization layer 50-1 as suggested in column 6, lines 55-67 and column 7, lines 1-8. In addition, multiple layers of data lines help to reduce the dimensions of border 90 as suggested in column 6, lines 11-13.
Yeh and Choi do not appear to specifically disclose wherein each of the connection lines comprises a first portion extending in the first direction and a second portion extending in a second direction perpendicular to the first direction, and wherein the first lines and the first portion are in the second conductive layer, and the second portion is in the first conductive layer.
However, in a related field of endeavor, Xu teaches display region includes a hollowed-out region (abstract) and further teaches wherein each of the connection lines comprises a first portion extending in the first direction and a second portion extending in a second direction perpendicular to the first direction (Figures 2-3 and [0044], 123 and 21), and wherein the first lines and the first portion are in the second conductive layer (Figures 2-3 and [0044], 123 and 122), and the second portion is in the first conductive layer (Figures 2-3, 21).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide connection lines as shown by Xu with the benefit that first data line 121, the second data line 122 and the auxiliary data line 123, for example, may be connected to the corresponding connection wire 21 through penetrating the via hole 22 of the insulating layer, thereby connecting the auxiliary data line 123 to the corresponding second data line 122 and connecting the auxiliary data line 123 to the corresponding first data line 121 as suggested in [0044] and figures 2-3.
Consider claim 1, it includes the limitations of claim 15 and thus rejected by the same reasoning.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 of U.S. Patent No. 12,156,441. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claims 1-3 of Patent
Claim 1 of this application
A display device comprising: a base part comprising a display area comprising a plurality of pixels each having at least one switching element and a light-emitting element including a first electrode electrically connected to the at least one switching element and an emissive layer on the first electrode,
A display device comprising: a base part comprising a display area comprising a plurality of pixels each having at least one switching element and a light-emitting element,
a non-display area surrounding the display area, a dead space area surrounded by the display area, and a through hole surrounded by the display area and the dead space area;
a non-display area surrounding the display area, and a through hole surrounded by the display area;
a plurality of first lines extending in a first direction on the base part and connected to the plurality of pixels;
a plurality of first lines extending in a first direction on the base part and connected to the plurality of pixels;
and connection lines bypassing the through hole and extending in the display area to connect between the first lines spaced apart from one another by the through hole among the plurality of first lines,
connection lines bypassing the through hole and extending in the display area to connect between the first lines spaced apart from one another by the through hole among the plurality of first lines.
wherein a connection line from among the connection lines bypassing the through hole comprises a plurality of portions on different layers, wherein the plurality of pixels and the plurality of first lines are located outside the dead space area, and wherein the dead space area further comprises a cathode cut disconnecting a cathode electrode of the light-emitting element, and a light blocking layer located on top of the cathode cut, the first electrode is not disposed in the dead space area and does not overlap the light blocking layer.
Claim 3: a first conductive layer comprising a first anode connection electrode connected to the at least one switching element; and a second conductive layer on the first conductive layer and comprising a second anode connection electrode connecting the first anode connection electrode with the light-emitting element, wherein the plurality of first lines and the second portion of each of the connection lines are in one of the first and second conductive layers, and the first portion of each of the connection lines is in the other of the first and second conductive layers.
a first conductive layer comprising a first anode connection electrode connected to the at least one switching element and a second conductive layer on the first conductive layer and comprising a second anode connection electrode connecting the first anode connection electrode with the light-emitting element, and wherein each of the connection lines comprises a first portion extending in the first direction and a second portion extending in a second direction perpendicular to the first direction, and wherein the first lines and the first portion are in the second conductive layer, and the second portion is in the first conductive layer.
As can be seen above, besides the wording, Patent includes all the limitations of claim 1.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see new reference Xu).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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