DETAILED ACTION
The current Office Action is in response to the papers submitted 06/15/2026. Claims 1 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 - 4 are objected to because of the following informalities:
Claim 3 is worded oddly to the examiner. It appears “correspond” in line 2 should be “corresponds”.
Claim 4 is worded oddly to the examiner. It appears “correspond” in line 2 should be “corresponds”.
Appropriate correction is required.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Barrow-Williams et al. (Pub. No.: US 2014/0123145) referred to as Barrow-Williams.
Regarding claim 1, Barrow-Williams teaches circuitry [202(0), Fig 2; 202, Fig 4A] to:
receive a memory access request from a requesting thread for a virtual storage location address [Fig 5; 810, Fig 8; Paragraph 0073; Threads generate requests to access a virtual address location. The request includes an ASID and virtual address information];
determine, using information indicated by one or more page tables, whether a physical storage location corresponding to the virtual storage location address is allocated to the requesting thread, wherein the information indicated by the one or more page tables comprises a thread identifier or access designator associated with the physical storage location [328, Fig 4A; Figs 4A – 6; Paragraphs 0036, 0046, 0050 - 0051, 0057 – 0058, 0073, 0081, and 0088; The tables in 328 are considered page tables that are used to map a request from a thread to a physical address using the ASID and virtual address information in the request from the thread. The ASID information identifies a thread since a thread is assigned an ASID. The ASID and other information, besides the physical address information, is access designators since they designate access to a physical address through mapping]; and
responsive to determining that the physical storage location is allocated to the requesting thread, cause the requesting thread to use the virtual storage location address to access the physical storage location [328, Fig 4A; Figs 4A – 6; Paragraphs 0036, 0046, 0050 - 0051, 0057 – 0058, 0073, 0081, and 0088; When there is a valid mapping for an ASID and virtual address of a thread to a physical address the ASID and virtual address is mapped to a specific virtual address in a specific table to access a specific physical address through the mapping].
Regarding claim 2, Barrow-Williams teaches physical storage locations [438, Fig 4D] are allocated to the requesting thread based, at least in part, on one or more memory requirements of the requesting thread [Paragraph 0088; The configuration of the threads is a memory requirement for the thread to use specific addresses].
Regarding claim 3, Barrow-Williams teaches virtual storage location address [436, Fig 4D] correspond to one or more allocations of the requesting thread [Paragraph 0088; The binding is an allocation of virtual addresses to threads].
Regarding claim 4, Barrow-Williams teaches the physical storage location [438, Fig 4D] correspond to one or more allocations of the requesting thread [Paragraph 0088; The physical addresses correspond to a thread through the binding allocation of the page table].
Regarding claim 5, Barrow-Williams teaches the information indicating whether the physical storage location [438, Fig 4D] are allocated to the one or more threads is generated by the one or more threads [840 , 850, and 852, Fig 8; Paragraph 0089; The hit or miss indications are generated by the threads using the virtual address and ASID to check the TLB to see if physical addresses in the TLB are allocated to thread].
Regarding claim 6, Barrow-Williams teaches one or more page tables store association data between thread identifiers and the allocated physical storage location [328, Fig 4A; Figs 4A – 6; The tables in 328 include mapping information that associates ASID thread identifiers to physical address using virtual address and page data bind identifier information].
Regarding Claim 7, Barrow-Williams teaches the one or more page tables indicate permissions to access the physical storage location [420(1), Fig 5; Paragraphs 0036, 0046, 0050 - 0051, 0057 – 0058, and 0088; The binding indicates what physical addresses a given thread has permission to access].
Claims 8 – 20 are system and method claims corresponding to claims 1 – 7 and are rejected using the same prior art and similar reasoning. Barrow-Williams teaches a system [100, Fig 1] comprising one or more processors [102 and 112, Fig 1].
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 8 – 10 that claim 1 is allowed since Barrow-Williams fails to teach page-table-indicated information itself comprises a thread identifier or access designator associated with a physical storage location or that such information is used to determine whether that physical storage location is allocated to a requesting thread. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
There is no mention of page-table-indicated information in the claims or specification. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., page-table-indicated information) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The page tables are the tables in MMU 328 in figure 4A. They are used to assign a physical and virtual address to a thread. The ASID is assigned by a thread thereby making the ASID assigned to a thread according to paragraph 0073. Figures 4B – 6 and associated text shows a thread sending a request to access memory. The request contains a virtual address and ASID. The ASID and virtual address are assigned to the thread that created them thereby identifying the thread. The page tables in MMU 328 are then used to map the ASID and virtual address to a physical address. The mapping tables determine if a physical address is mapped to a thread. A valid mapping being present is a determination that a virtual and physical address are assigned to the thread that sent the virtual address and ASID.
The paging tables in MMU 328 includes entries such as ASID, virtual address, and physical address. The ASID is considered a thread identifier since each thread request includes an ASID which is used to assign a thread to a certain set of virtual and physical addresses. This assignment defines a thread and therefor the ASID identifies a thread or threads assigned to specific virtual and physical addresses. The virtual and physical addresses can also be considered access designators since they designate certain locations in memory that a thread can access.
The applicant argues on page 10 that the remaining independent claims are allowed for containing similar limitations argues allowable with regard to claim 1 above. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments above regarding claim 1 showing how the prior art teaches the argued limitations. The remaining independent claims are rejected in a similar manner as claim 1.
The applicant argues on pages 10 – 11 that the remaining dependent claims are allowable for being dependent on the argued allowable independent claims above. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding the independent claims explaining how the prior art teaches the limitations of the independent claims. The dependent claims are rejected based in part on the rejections of their related independent claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Christopher D Birkhimer/Primary Examiner, Art Unit 2136
Prosecution Insights