CTNF 18/959,239 CTNF 84777 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-05 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle , 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 05/19/2026 has been entered. DETAILED ACTION Claims 1 – 20 are pending. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 05/19/2026 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 – 7 and 10 – 20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Semiao et al., "SRAM Performance Sensor", 2021 XXXVI CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS), IEEE, 24 November 2021 (2021-11-24) . Regarding claim 1, Semiao discloses: A method for operating a memory, comprising: sensing a bit line signal for a bit line of the memory transitioning between a first state and a second state when data is read from one or more memory cells of the memory or when data is written to the one or more memory cells of the memory (section II.B, II.B.1; figure 2); detecting a timing margin error in the memory based, at least in part, on a delay associated with the bit line signal transitioning between the first state and the second state (section II.B.1, II.B.2, II.B.3); and adjusting a parameter associated with the memory to compensate for the timing margin error (Introduction, section II.B). Regarding claim 2, Semiao discloses: generating a pulse signal having a pulse width that is proportional to the delay associated with the bit line signal transitioning between the first state and the second state (section II.B.1); converting the pulse signal to a sensed voltage based, at least in part, on the pulse width (section II.B.2); comparing the sensed voltage to a reference voltage that is lower than a supply voltage for the memory (section II.B.2); and predicting the timing margin error based on the comparing indicating the sensed voltage is greater than the reference voltage (section II.B.3). Regarding claim 3, Semiao discloses: adjusting a sensitivity of a sensor configured to generate the pulse signal, the sensitivity of the sensor adjusted based on one or more operating conditions for the local memory (section II.B, II.B.1; figure 2); and sensing, using the adjusted sensor, the bit line signal transitioning between the first state and the second state (section II.B, II.B.1, II.B.2; figure 2). Regarding claim 4, Semiao discloses: configuring a finite state machine in a first state of a plurality of different states in response to generating the pulse signal, wherein the comparing occurs in response to configuring the finite state machine in the first state (section II.B, II.B.4). Regarding claim 5, Semiao discloses: converting the pulse signal to the sensed voltage comprises charging a capacitor to a voltage level that is proportional to the pulse width (section II.B.2). Regarding claim 6, Semiao discloses: adjusting a parameter to compensate for the timing margin error comprises: determining a current power mode for the memory, the current power mode corresponding to one of a plurality of different power modes in which the memory is configurable (Introduction, section II.B, II.B.2); and increasing a voltage at a memory rail of the memory from a first voltage to a second voltage based on the current power mode for the memory (Introduction, section II.B, II.B.2). Regarding claim 7, Semiao discloses: determining whether the timing margin error is still detected in the memory (section II.B.2, II.B.3); and decreasing the voltage at the memory rail from the second voltage to a third voltage that is greater than the first voltage, in response to determining the timing margin error is no longer detected in the memory (section II.B.2, II.B.3). Regarding claim 10, Semiao discloses: A timing margin monitor for detecting timing margin errors in a memory array, the timing margin monitor comprising: a transition detector having an input coupled to a bit line of the memory array, the transition detector configured to output a pulse signal having a width corresponding to a delay associated with a bit line signal on the bit line transitioning between a first logic state and a second logic state (section II.B.1, II.B.2, II.B.3); a pulse detector configured to generate a sensed voltage signal based on the pulse signal, the sensed voltage signal having a voltage value corresponding to the width of the pulse signal (section II.B.1, II.B.2, II.B.3); and a comparator configured to determine whether a timing margin error exists in the memory array based on the sensed voltage signal and a reference voltage signal (section II.B.1, II.B.2, II.B.3). Regarding claim 11, Semiao discloses: the transition detector comprises: a first chain of inverters coupled to the input (figure 3); a second chain of inverters coupled to the input (figure 3); and an exclusive or (XOR) gate having a first input and a second input, the first input coupled to an output of the first chain of inverters, the second input coupled to an output of the second chain of inverters (figure 3). Regarding claim 12, Semiao discloses: the transition detector further comprises: a not or (NOR) gate having a first input coupled to an output of the XOR gate, the NOR gate having a second input coupled to an output of a sense amplifier connected to the bit line (figure 4); and an inverter having an input coupled to an output of the NOR gate, the inverter configured to output the pulse signal (figure 4). Regarding claim 13, Semiao discloses: the comparator is configured to output a timing margin error signal when a sensed voltage indicated by the sensed voltage signal is greater than a reference voltage indicated by the reference voltage signal (section II.B.3, II.B.4). Regarding claim 14, Semiao discloses: an output of the comparator is coupled to a timing margin controller included in a controller for the memory array, wherein the timing margin controller is configured to implement a dynamic compensation scheme to compensate for the timing margin error indicated by the timing margin error signal (section II.B.3, II.B.4). Regarding claim 15, Semiao discloses: a finite state machine (FSM) controller configured to transition from a first state to a second state upon receiving an interrupt signal from the transition detector (section II.B, II.B.4). Regarding claim 16, Semiao discloses: in the second state, the FSM controller is configured to output a control signal to activate the comparator to determine whether the timing margin error exists in the memory array (section II.B.3, II.B.4). Regarding claim 17, Semiao discloses: the transition detector is configured to generate the interrupt signal to indicate to the FSM controller that the transition detector detected a pulse (section II.B, II.B.4). Regarding claim 18, Semiao discloses: a reference voltage indicated by the reference voltage signal is less than a supply voltage for the memory array (section II.B, II.B.4). Regarding claim 19, Semiao discloses: the pulse detector is configurable in a plurality of different sensitivity settings associated with detecting the timing margin error (section II.B.1, II.B.2). Regarding claim 20, Semiao discloses: An apparatus comprising: means for sensing a bit line signal for a bit line of a memory transitioning between a first state and a second state when data is read from one or more memory cells of the memory or when data is written to the one or more memory cells of the memory (section II.B, II.B.1; figure 2); means for detecting a timing margin error in the memory based, at least in part, on a delay associated with the bit line signal transitioning between the first state and the second state (section II.B.1, II.B.2, II.B.3); and means for adjusting a parameter associated with the memory to compensate for the timing margin error (Introduction, section II.B) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : LEE; Jong-Pil et al. US 20150287444 A1 Pal; Dipti Ranjan et al. US 11249530 B1 Thorne; Neil Kenneth US 8560907 B1 Cho; Minki et al. US 20180287592 A1 Berke; Stuart Allen et al. US 20110231697 A1 Nandanwar; et al. US 20250279772 A1 Kim; Jaeil US 11164620 B1 Lang; Murong et al. US 20220137854 A1 Shohara; Aki et al. US 6473607 B1 WATANABE; Hiroyuki et al. US 20230081996 A1 YU; Jun et al. US 20230402121 A1 detecting a timing margin error in the memory based, at least in part, on a delay associated with the bit line signal transitioning between the first state and the second state Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Daniel F. McMahon/Primary Examiner, Art Unit 2111 Application/Control Number: 18/959,239 Page 2 Art Unit: 2111
Prosecution Insights