DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6-11, 15-16, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG et al (US Pub 2021/0012708) in view of Zou et al (US Pub 2021/0366352) and BYUN (US Pub 2016/0117987).
With respect to claim 1, YANG discloses a driver including a plurality of stages, (fig. 5; discloses a driver 420 comprising plurality of stages STA1-STA4) at least one stage of the plurality of stages comprising: an input circuit configured to transfer an input signal to a first node in response to at least one of a clock signal and an inverted clock signal (fig. 22; node controller NC; par 0116; discloses the node controller NC of the kth stage STAk may apply a start signal or carry signal, which is input to the start terminal ST, to the first node N1 in response to a clock signal input to the clock terminal CT; par 0154; discloses The fourth inverter INV4 is connected between the node controller NC and the clock terminal CT. The fourth inverter INV4 of the k.sup.th stage STAk may be connected between the gate electrode of the third node control transistor NC3 and the clock terminal CT. The fourth inverter INV4 of the (k+1).sup.th stage STAk+1 may be connected between the gate electrode of the fourth node control transistor NC4 and the clock terminal CT. The fourth inverter INV4 may invert a clock signal CLK input to the clock terminal CT and apply the inverted clock signal CLK to the node controller NC); a holding capacitor configured to hold a voltage of the first node (fig. 22; capacitor C; par 0115; discloses the capacitor C may be connected between the first node N1 and the gate low voltage terminal VLT to maintain a voltage of the first node N1); a first inverter configured to generate a voltage of a second node by inverting the voltage of the first node (fig. 22; inverter INV1; par 0106; discloses The first inverter INV1 is connected between a first node N1 and a second node N2. The first inverter INV1 may invert a voltage of the first node N1 and apply the inverted voltage to the second node N2); a second inverter configured to generate a voltage of a third node by inverting the voltage of the second node (fig. 22; inverter INV2; par 0109; discloses he second inverter INV2 is connected between the second node N2 and the output terminal OUT. The second inverter INV2 may invert a voltage of the second node N2 and may apply the inverted voltage to the output terminal OUT); a third inverter configured to generate a carry signal by inverting the voltage of the second node (fig. 22; Inverter INV3; par 0112; discloses the third inverter INV3 is connected between the second node N2 and the carry signal terminal COUT. The third inverter INV3 may invert a voltage of the second node N2 and may apply the inverted voltage to the carry signal terminal COUT); and wherein at least one of the first inverter, the second inverter, the third inverter includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series (par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors; fig. 8; discloses transistors T1 and T2 connected in series; transistors T3 and T4 connected in series and transistors T5 and T6 connected in series);
YANG doesn’t expressly disclose an output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal; wherein at least one the output control circuit includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series;
In the same field of endeavor, Zou discloses a gate driver for a display device where each stage of the gate driver includes an output circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal (fig. 7A; discloses output circuit 100m connected to the output of stage 201_m, receiving output 1_m at Crt1_m, and control signal at Ctr2_m and generating output 2_m); wherein at least one the output control circuit includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series (fig. 4B ; discloses circuit for 100_m comprising transistor T1 and T2 connected in series; par 0125; discloses he N-type transistor is used in the first conversion subcircuit 110, and the P-type transistor is used in the second conversion subcircuit 120, and vice versa);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG to incorporate the teachings of Zou to include and output circuit supplying the output signal to the gate lines of the display panel in order to keep synchronous the phases of the signal before and after level conversion while guaranteeing the level conversion by the level conversion circuit taking an output signal generated by the scan signal generation circuit as a trigger signal, thereby meeting voltage requirements of the display panel;
YANG as modified by Zou don’t expressly disclose wherein the plurality of stages include plurality of output control circuits, respectively, and the plurality of output control circuits receive the same output enable signal;
In the same field of endeavor, BYUN discloses display device and driving method (see abstract); BYUN discloses the gate driver comprising plurality of stages (fig. 1; gate driver 140 comprises plurality of stages GOU1-GOUN); wherein the plurality of stages include plurality of output control circuits, respectively, and the plurality of output control circuits receive the same output enable signal (par 0044; discloses an output control signal GPS may be applied to the output control terminal GP. The output control signal GPS may be simultaneously applied to each output control terminal GP of all gate drivers GDU1, GDU2, GDU3, GDU4, . . . , to control the overall display panel 120; fig. 2; discloses each stages of the gate driver is connected to same gate control signal GPS);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou to incorporate the teachings of BYUN to use the same output control signal for plurality of stages in order to reduce the number of output control signal while still outputting the gate signals to the plurality of gate lines sequentially.
With respect to claim 6, YANG as modified by Zou and BYUN discloses wherein the output control circuit includes: a first PMOS transistor including a gate which receives the output enable signal, a first terminal connected to the third node, and a second terminal connected to an output node at which the output signal is output; and a first NMOS transistor including a gate which receives the output enable signal, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the output node (Zhou; see fig. 4B; discloses output circuit 100_m includes a first transistor T1 with gate receiving enable signal Ctr1_m, first electrode receiving power and second terminal connected to output and a second transistor T2 with gate receiving enable signal Ctr1_m, a first electrode receiving low voltage VGL and second electrode connected to output; par 0125; discloses the N-type transistor is used in the first conversion subcircuit 110, and the P-type transistor is used in the second conversion subcircuit 120, and vice versa).
With respect to claim 7, YANG as modified by Zou and BYUN discloses wherein the input circuit includes at least one of a second PMOS transistor including a gate which receives the inverted clock signal, a first terminal which receives the input signal, and a second terminal connected to the first node, (YANG; fig. 22; a NC3 with gate receiving inverted clock CT , a first electrode receiving ST signal and second terminal connected to node N1) and a second NMOS transistor including a gate which receives the clock signal, a first terminal which receives the input signal, and a second terminal connected to the first node (YANG; fig. 22; discloses a NC1 includes a first transistor with gate receiving a clock CT, a first terminal receiving ST signal and output connected to node N1).
With respect to claim 8, YANG as modified by Zou and BYUN discloses wherein the holding capacitor includes a first electrode connected to a line which transfers a high gate voltage, and a second electrode connected to the first node (YANG; fig. 22; discloses capacitor C connected between the N1 and the power VLT; par 0161; discloses a capacitor of each of the stages of the emission signal driver is connected to a first node, a gate high voltage and a gate low voltage may be output to each of output terminals without bootstrapping).
With respect to claim 9, YANG as modified by Zou and BYUN discloses wherein the first inverter includes: a third PMOS transistor including a gate connected to the first node, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the second node (YANG; fig. 24; discloses inverter 1 includes a transistor T1 with gate connected to first node N1, a first terminal connected to power VHT and a second electrode connected to second node N2); and a third NMOS transistor including a gate connected to the first node, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the second node (YANG; fig. 24; discloses inverter 1 further includes a transistor T2 with gate connected to node 1, first electrode connected to power VLT and second electrode connected to second node N2; see par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors).
With respect to claim 10, YANG as modified by Zou and BYUN discloses wherein the second inverter includes: a fourth PMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the third node (YANG; fig. 24; discloses inverter 2 includes a transistor T3 with gate connected to first node N2, a first terminal connected to power VHT and a second electrode connected to second node out (i.e. third node)); and a fourth NMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the third node (YANG; fig. 24; discloses inverter 2 further includes a transistor T4 with gate connected to first node N2, a first terminal connected to power VLT and a second electrode connected to second node out (i.e. third node); see par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors).
With respect to claim 11, YANG as modified by Zou and BYUN discloses wherein the third inverter includes: a fifth PMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to a carry node at which the carry signal is output (YANG; fig. 24; discloses inverter 3 includes a transistor T5 with gate connected to first node N2, a first terminal connected to power VHT and a second electrode connected to Cout (i.e. carry out signal)); and a fifth NMOS transistor including a gate connected to the second node, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the carry node (YANG; fig. 24; discloses inverter 3 further includes a transistor T6 with gate connected to first node N2, a first terminal connected to power VLT and a second electrode connected to Cout (i.e. carry out signal); see par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors).
With respect to claim 15, YANG as modified by Zou and BYUN discloses wherein the output control circuit outputs the voltage of the third node as the output signal while the output enable signal has a high level, and outputs a low gate voltage as the output signal while the output enable signal has a low level (Zhou; fig. 7B and 8; discloses when the control signal OUT1_m is high, the output out2_m is high which corresponds to the input voltage VGH and when the OUT1_m is low, the output out2_m is low).
With respect to claim 16, YANG as modified by Zou and BYUN discloses wherein the output control circuit includes: a first NMOS transistor including a gate which receives the output enable signal, a first terminal connected to the third node, and a second terminal connected to an output node at which the output signal is output; and a first PMOS transistor including a gate which receives the output enable signal, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the output node (Zhou; see fig. 4B; discloses output circuit 100_m includes a first transistor T1 with gate receiving enable signal Ctr1_m, first electrode receiving power and second terminal connected to output and a second transistor T2 with gate receiving enable signal Ctr1_m, a first electrode receiving low voltage VGL and second electrode connected to output; par 0125; discloses the N-type transistor is used in the first conversion subcircuit 110, and the P-type transistor is used in the second conversion subcircuit 120, and vice versa ).
With respect to claim 19, YANG discloses an electronic device comprising: a processor configured to provide input image data; and a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device comprising (fig. 1; device 10; par 0057; discloses Referring to FIGS. 1 to 3, an embodiment of the display device 10 is a device which displays moving images or static images and may be used as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (“PC”), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (“PMP”), a navigation device, and an ultra-mobile PC, and various products such as a television set, a notebook, a monitor, a billboard, and an Internet of Things (“IoT”) product, for example; par 0070; discloses the timing controller 210 receives digital video data DATA and timing signals from the circuit board 300): a display panel including a plurality of pixels (fig. 3; discloses panel 100 with plurality of pixels SP); a data driver configured to provide data signals to the plurality of pixels (fig. 3; data driver 220; par 0071; discloses the data driver 220 converts the digital video data DATA to analog positive/negative data voltages and outputs the analog positive/negative data voltages to the data lines DL through the fan-out lines FL. When the sub-pixels SP are selected (or turned on) in response to the scan signals of the scan driving circuit 400, the data voltages are supplied to the selected sub-pixels SP); a gate driver configured to provide gate signals to the plurality of pixels (fig. 3; scan driver; par 0067; discloses The scan signal driver 410 may generate the scan signals based on the scan control signals SCS and sequentially output the scan signals to the scan lines SL. The emission signal driver 420 generates emission signals based on the emission control signals ECS and sequentially outputs emission control signals to the emission lines EL); an emission driver configured to provide emission signals to the plurality of pixels (fig. 3; emission control driver 420; see par 0067); and a controller configured to control the data driver, the gate driver and the emission driver, (fig. 3; Timing controller 210; par 0070; discloses the timing controller 210 may generate the scan control signals SCS for controlling operation timings of the scan signal driver 410 based on the timing signals, the emission control signal ECS for controlling operation timings of the emission signal driver 420 based on the timing signals, and data control signals DCS for controlling operation timings of the data driver 220 based on the timing signals ) wherein at least one of the gate driver and the emission driver includes a plurality of stages, (see fig. 5; discloses driver 420 with plurality of stages) and wherein at least one stage of the plurality of stages comprises: an input circuit configured to transfer an input signal to a first node in response to at least one of a clock signal and an inverted clock signal (fig. 22; node controller NC; par 0116; discloses the node controller NC of the kth stage STAk may apply a start signal or carry signal, which is input to the start terminal ST, to the first node N1 in response to a clock signal input to the clock terminal CT; par 0154; discloses The fourth inverter INV4 is connected between the node controller NC and the clock terminal CT. The fourth inverter INV4 of the k.sup.th stage STAk may be connected between the gate electrode of the third node control transistor NC3 and the clock terminal CT. The fourth inverter INV4 of the (k+1).sup.th stage STAk+1 may be connected between the gate electrode of the fourth node control transistor NC4 and the clock terminal CT. The fourth inverter INV4 may invert a clock signal CLK input to the clock terminal CT and apply the inverted clock signal CLK to the node controller NC); a holding capacitor configured to hold a voltage of the first node (fig. 22; capacitor C; par 0115; discloses the capacitor C may be connected between the first node N1 and the gate low voltage terminal VLT to maintain a voltage of the first node N1); a first inverter configured to generate a voltage of a second node by inverting the voltage of the first node (fig. 22; inverter INV1; par 0106; discloses The first inverter INV1 is connected between a first node N1 and a second node N2. The first inverter INV1 may invert a voltage of the first node N1 and apply the inverted voltage to the second node N2); a second inverter configured to generate a voltage of a third node by inverting the voltage of the second node (fig. 22; inverter INV2; par 0109; discloses he second inverter INV2 is connected between the second node N2 and the output terminal OUT. The second inverter INV2 may invert a voltage of the second node N2 and may apply the inverted voltage to the output terminal OUT); a third inverter configured to generate a carry signal by inverting the voltage of the second node (fig. 22; Inverter INV3; par 0112; discloses the third inverter INV3 is connected between the second node N2 and the carry signal terminal COUT. The third inverter INV3 may invert a voltage of the second node N2 and may apply the inverted voltage to the carry signal terminal COUT); and wherein at least one of the first inverter, the second inverter, the third inverter includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series (par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors; fig. 8; discloses transistors T1 and T2 connected in series; transistors T3 and T4 connected in series and transistors T5 and T6 connected in series);
YANG doesn’t expressly disclose an output control circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal; wherein at least one the output control circuit includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series;
In the same field of endeavor, Zou discloses a gate driver for a display device where each stage of the gate driver includes an output circuit configured to selectively output the voltage of the third node as an output signal in response to an output enable signal (fig. 7A; discloses output circuit 100m connected to the output of stage 201_m, receiving output 1_m at Crt1_m, and control signal at Ctr2_m and generating output 2_m); wherein at least one the output control circuit includes a p-type metal-oxide-semiconductor (PMOS) transistor and an n-type metal-oxide-semiconductor (NMOS) transistor that are connected in series (fig. 4B ; discloses circuit for 100_m comprising transistor T1 and T2 connected in series; par 0125; discloses he N-type transistor is used in the first conversion subcircuit 110, and the P-type transistor is used in the second conversion subcircuit 120, and vice versa);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG to incorporate the teachings of Zou to include and output circuit supplying the output signal to the gate lines of the display panel in order to keep synchronous the phases of the signal before and after level conversion while guaranteeing the level conversion by the level conversion circuit taking an output signal generated by the scan signal generation circuit as a trigger signal, thereby meeting voltage requirements of the display panel;
YANG as modified by Zou don’t expressly disclose wherein the plurality of stages include plurality of output control circuits, respectively, and the plurality of output control circuits receive the same output enable signal;
In the same field of endeavor, BYUN discloses display device and driving method (see abstract); BYUN discloses the gate driver comprising plurality of stages (fig. 1; gate driver 140 comprises plurality of stages GOU1-GOUN); wherein the plurality of stages include plurality of output control circuits, respectively, and the plurality of output control circuits receive the same output enable signal (par 0044; discloses an output control signal GPS may be applied to the output control terminal GP. The output control signal GPS may be simultaneously applied to each output control terminal GP of all gate drivers GDU1, GDU2, GDU3, GDU4, . . . , to control the overall display panel 120; fig. 2; discloses each stages of the gate driver is connected to same gate control signal GPS);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou to incorporate the teachings of BYUN to use the same output control signal for plurality of stages in order to reduce the number of output control signal while still outputting the gate signals to the plurality of gate lines sequentially.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG et al (US Pub 2021/0012708) in view of Zou et al (US Pub 2021/0366352), BYUN (US Pub 2016/0117987) and CHOI (US Pub 2023/0006013).
With respect to claim 2, YANG as modified by Zhou and BYUN don’t expressly disclose wherein a first active region of the PMOS transistor includes a material different from a material of a second active region of the NMOS transistor;
In the same field of endeavor, CHOI discloses display device comprising plurality of transistors (see abstract); CHOI discloses wherein a first active region of the PMOS transistor includes a material different from a material of a second active region of the NMOS transistor (par 0112; discloses The semiconductor layer (first semiconductor layer 100) of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, which are PMOS transistors, and the semiconductor layer (second semiconductor layer 400) of the third transistor T3 and the fourth transistor T4, which are NMOS transistors, may be disposed in different layers from each other and may include different materials from each other; see par 0097 as well);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zhou and BYUN to incorporate the teachings of CHOI to include transistor of different types in the gate driver in order to include transistor with good characteristics such that unwanted leakage of the current is reduced and operation of the display device is improved.
With respect to claim 3, YANG as modified by Zhou, BYUN and CHOI discloses wherein the first active region of the PMOS transistor includes polycrystalline silicon, (CHOI; par 0141; discloses the first semiconductor layer 100 may include polycrystalline silicon) and wherein the second active region of the NMOS transistor includes an oxide semiconductor, an organic semiconductor or amorphous silicon (CHOI; par 0145; discloses the second semiconductor layer 400 may include an oxide semiconductor).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG et al (US Pub 2021/0012708) in view of Zou et al (US Pub 2021/0366352), BYUN (US Pub 2016/0117987) and CHOI (US Pub 2023/0006013) and Yamazaki (US Pub 2006/0068536).
With respect to claim 4, YANG as modified by Zou, BYUN and CHOI discloses a low gate voltage is applied to a terminal of the NMOS transistor (fig. 24; discloses an electrode of the transistor T2 is connected low voltage VLT);
YANG as modified by Zou, BYUN and CHOI don’t expressly disclose wherein the NMOS transistor includes a top gate located above the second active region, and a bottom gate located below the second active region, and wherein a low gate voltage is applied to a terminal of the NMOS transistor, and a second low gate voltage lower than the low gate voltage is applied to the bottom gate of the NMOS transistor;
In the same field of endeavor, Yamazaki discloses NMOS transistor includes a top gate located above the second active region, and a bottom gate located below the second active region, and wherein a low gate voltage is applied to a terminal of the NMOS transistor, and a second low gate voltage lower than the low gate voltage is applied to the bottom gate of the NMOS transistor (par 0114; discloses the invention provides a semiconductor device having an n-type thin film transistor 116 including two gate electrodes of a conductive layer 181 functioning as a bottom gate electrode and a conductive layer 183 functioning as a top gate electrode. A method for applying a bias voltage to the conductive layers 181 and 182 functioning as a bottom gate electrode is effective in order to control the power consumption. More specifically, applying negative bias voltage to the conductive layer 181 of the n-type thin film transistor 116 functioning as a bottom gate electrode enables the threshold voltage to increase and the leakage current to reduce);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou, BYUN and CHOI to incorporate the teachings of Yamazaki to include dual gate NMOS transistor in the inverter circuits with negative biasing voltage in order to reduce the leakage current in the transistors such that operating condition of the transistors is improved.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG et al (US Pub 2021/0012708) in view of Zou et al (US Pub 2021/0366352), BYUN (US Pub 2016/0117987) and WU et al (US Pub 2017/0287424).
With respect to claim 5, YANG as modified by Zou and BYUN don’t expressly disclose wherein the output control circuit outputs a low gate voltage as the output signal while the output enable signal has a high level, and outputs the voltage of the third node as the output signal while the output enable signal has a low level;
In the same field of endeavor, WU discloses shift register for display device and driving method (see abstract); WU discloses output circuit connected to each stage of the plurality of stages (see fig. 7; output circuit NOR1, AND3); WU discloses wherein the output control circuit outputs a low gate voltage as the output signal while the output enable signal has a high level, and outputs the voltage of the third node as the output signal while the output enable signal has a low level (see fig. 7 and 8; discloses when enable signal CLK5 is low, the output L1 is corresponds to input N2 and when enable signal is high, the output is low);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou and BYUN to incorporate the teachings of WU to include output circuit at each stages of shift driver in order to generate output signal to scan plurality of scan lines while reducing the gate driver area and facilitating border narrowing of the display device.
Claim(s) 12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG et al (US Pub 2021/0012708) in view of Zou et al (US Pub 2021/0366352), BYUN (US Pub 2016/0117987) and Akiyoshi (US Pub 2003/0234671).
With respect to claim 12, YANG as modified by Zou and BYUN don’t expressly disclose wherein the at least one stage further comprises: a sixth PMOS transistor including a gate which receives a global reset signal, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the first node;
In the same field of endeavor, Akiyoshi discloses pulse generating circuit (see abstract); Akiyoshi discloses wherein the at least one stage further comprises: a sixth PMOS transistor including a gate which receives a global reset signal, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the first node (fig. 6; discloses reset transistor P35 with gate connected to reset signal, a first electrode connected to power and second electrode connected to first node N21; par 0044; discloses Reset transistors P35, N36 and P37 for being driven by the leading edge of the propagated reset pulse RESET and for driving the trailing edge of the propagating set pulse SET are provided respectively at an output terminal of each inverter in the first inverter array INV10-13. Since these reset transistors are driven by the leading edge of the propagated reset pulse RESET at the same timing as or an earlier timing than the trailing edge of the propagating set pulse SET, the trailing edge of the propagating set pulse SET can be prevented from delaying by driving steeply the trailing edge of the propagating set pulse);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou and BYUN to incorporate the teachings of Akiyoshi to include a reset transistor connected to first node in order to prevent signal delay in each stages of the gate driver.
With respect to claim 17, YANG discloses a driver including a plurality of stages, at least one stage of the plurality of stages comprising (fig. 5; discloses a driver 420 comprising plurality of stages STA1-STA4): a second PMOS transistor including a gate which receives an inverted clock signal, a first terminal which receives an input signal, and a second terminal connected to a first node (YANG; fig. 22; a NC3 with gate receiving inverted clock CT , a first electrode receiving ST signal and second terminal connected to node N1); a second NMOS transistor including a gate which receives a clock signal, a first terminal which receives the input signal, and a second terminal connected to the first node (YANG; fig. 22; discloses a NC1 includes a first transistor with gate receiving a clock CT, a first terminal receiving ST signal and output connected to node N1); a holding capacitor including a first electrode connected to a line which transfers a high gate voltage, and a second electrode connected to the first node (YANG; fig. 22; discloses capacitor C connected between the N1 and the power VLT; par 0161; discloses a capacitor of each of the stages of the emission signal driver is connected to a first node, a gate high voltage and a gate low voltage may be output to each of output terminals without bootstrapping); a third PMOS transistor including a gate connected to the first node, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to a second node (YANG; fig. 24; discloses inverter 1 includes a transistor T1 with gate connected to first node N1, a first terminal connected to power VHT and a second electrode connected to second node N2); a third NMOS transistor including a gate connected to the first node, a first terminal connected to the line which transfers the low gate voltage, and a second terminal connected to the second node (YANG; fig. 24; discloses inverter 1 further includes a transistor T2 with gate connected to node 1, first electrode connected to power VLT and second electrode connected to second node N2; see par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors); a fourth PMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to the third node (YANG; fig. 24; discloses inverter 2 includes a transistor T3 with gate connected to first node N2, a first terminal connected to power VHT and a second electrode connected to second node out (i.e. third node)); a fourth NMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the low gate voltage, and a second terminal connected to the third node (YANG; fig. 24; discloses inverter 2 further includes a transistor T4 with gate connected to first node N2, a first terminal connected to power VLT and a second electrode connected to second node out (i.e. third node); see par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors); a fifth PMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to a carry node (YANG; fig. 24; discloses inverter 3 includes a transistor T5 with gate connected to first node N2, a first terminal connected to power VHT and a second electrode connected to Cout (i.e. carry out signal)); a fifth NMOS transistor including a gate connected to the second node, a first terminal connected to the line which transfers the low gate voltage, and a second terminal connected to the carry node (YANG; fig. 24; discloses inverter 3 further includes a transistor T6 with gate connected to first node N2, a first terminal connected to power VLT and a second electrode connected to Cout (i.e. carry out signal); see par 0105; discloses first, third and fifth transistors T1, T3 and T5, and a second node control transistor NC2 may be P-type transistors, and second, fourth, and sixth transistors T2, T4 and T6, and a first node control transistor NC1 may be N-type transistors);
YANG doesn’t expressly disclose a first PMOS transistor including a gate which receives an output enable signal, a first terminal connected to a third node, and a second terminal connected to an output node; a first NMOS transistor including a gate which receives the output enable signal, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the output node;
In the same field of endeavor, Zou discloses a gate driver for a display device where each stage of the gate driver includes an output circuit (fig. 7A; circuit 100_m); a first PMOS transistor including a gate which receives an output enable signal, a first terminal connected to a third node, and a second terminal connected to an output node; a first NMOS transistor including a gate which receives the output enable signal, a first terminal connected to a line which transfers a low gate voltage, and a second terminal connected to the output node (see fig. 4B; discloses output circuit 100_m includes a first transistor T1 with gate receiving enable signal Ctr1_m, first electrode receiving power and second terminal connected to output and a second transistor T2 with gate receiving enable signal Ctr1_m, a first electrode receiving low voltage VGL and second electrode connected to output; par 0125; discloses the N-type transistor is used in the first conversion subcircuit 110, and the P-type transistor is used in the second conversion subcircuit 120, and vice versa);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG to incorporate the teachings of Zou to include and output circuit supplying the output signal to the gate lines of the display panel in order to keep synchronous the phases of the signal before and after level conversion while guaranteeing the level conversion by the level conversion circuit taking an output signal generated by the scan signal generation circuit as a trigger signal, thereby meeting voltage requirements of the display panel;
YANG as modified by Zou don’t expressly disclose a sixth PMOS transistor including a gate which receives a global reset signal, a first terminal connected to the line which transfers the high gate voltage, and a second terminal connected to the first node;
In the same field of endeavor, Akiyoshi discloses pulse generating circuit (see abstract); Akiyoshi discloses wherein the at least one stage further comprises: a sixth PMOS transistor including a gate which receives a global reset signal, a first terminal connected to a line which transfers a high gate voltage, and a second terminal connected to the first node (fig. 6; discloses reset transistor P35 with gate connected to reset signal, a first electrode connected to power and second electrode connected to first node N21; par 0044; discloses Reset transistors P35, N36 and P37 for being driven by the leading edge of the propagated reset pulse RESET and for driving the trailing edge of the propagating set pulse SET are provided respectively at an output terminal of each inverter in the first inverter array INV10-13. Since these reset transistors are driven by the leading edge of the propagated reset pulse RESET at the same timing as or an earlier timing than the trailing edge of the propagating set pulse SET, the trailing edge of the propagating set pulse SET can be prevented from delaying by driving steeply the trailing edge of the propagating set pulse);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou to incorporate the teachings of Akiyoshi to include a reset transistor connected to first node in order to prevent signal delay in each stages of the gate driver;
YANG as modified by Zou and Akiyoshi don’t expressly disclose wherein the plurality of stages include plurality of output control circuits, respectively, and the plurality of output control circuits receive the same output enable signal;
In the same field of endeavor, BYUN discloses display device and driving method (see abstract); BYUN discloses the gate driver comprising plurality of stages (fig. 1; gate driver 140 comprises plurality of stages GOU1-GOUN); wherein the plurality of stages include plurality of output control circuits, respectively, and the plurality of output control circuits receive the same output enable signal (par 0044; discloses an output control signal GPS may be applied to the output control terminal GP. The output control signal GPS may be simultaneously applied to each output control terminal GP of all gate drivers GDU1, GDU2, GDU3, GDU4, . . . , to control the overall display panel 120; fig. 2; discloses each stages of the gate driver is connected to same gate control signal GPS);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou and Akiyoshi to incorporate the teachings of BYUN to use the same output control signal for plurality of stages in order to reduce the number of output control signal while still outputting the gate signals to the plurality of gate lines sequentially.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG et al (US Pub 2021/0012708) in view of Zou et al (US Pub 2021/0366352), BYUN (US Pub 2016/0117987) and YANG et al (US Pub 2021/0118375) referred to as YANG375.
With respect to claim 13, YANG as modified by Zou and BYUN don’t expressly disclose wherein the at least one stage further comprises: a PMOS boosting buffer, wherein the voltage of the first node has a low level, and the PMOS boosting buffer is configured to output a low gate voltage to the third node;
In the same field of endeavor, YANG375 discloses display device and driving method thereof (see abstract); wherein the at least one stage further comprises: a PMOS boosting buffer, wherein the voltage of the first node has a low level, and the PMOS boosting buffer is configured to output a low gate voltage to the third node (par 0119; discloses The buffer BUF may supply a voltage of the second node N2 to the first output terminal OUT1 based on an input signal of the second clock terminal CT2. In such an embodiment, the first output terminal OUT1 of the k.sup.th stage STG(k) may be connected to a third node N3 connected between the buffer BUF and the second inverter INV2. The buffer BUF of the k.sup.th stage STG(k) may output a carry signal CR(k) through the first output terminal OUT1);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou and BYUN to incorporate the teachings of YANG375 to include a buffer circuit within each stage of the scan driver in order to improve the current capability of the scan driver and reduce power consumption such that reliability of the display device is improved.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG et al (US Pub 2021/0012708) in view of Zou et al (US Pub 2021/0366352), BYUN (US Pub 2016/0117987) and PARK et al (US Pub 2021/0027707).
With respect to claim 20, YANG as modified by Zou and BYUN don’t expressly disclose wherein the display panel includes a first panel region driven at a first driving frequency, and a second panel region driven at a second driving frequency lower than the first driving frequency, wherein, in a first frame period, the controller generates the output enable signal having a first level during a first time within the first frame period allocated to the first panel region and a second time within the first frame period allocated to the second panel region such that the plurality of stages outputs output signals to both of the first panel region and the second panel region, and wherein, in a second frame period, the controller generates the output enable signal having the first level during a third time within the second frame period allocated to the first panel region and a second level different from the first level during a fourth time within the second frame period allocated to the second panel region such that the plurality of stages outputs the output signals to the first panel region and does not output the output signals to the second panel region;
In the same field of endeavor, PARK discloses display device and driving method (see abstract); PARK discloses wherein the display panel includes a first panel region driven at a first driving frequency, and a second panel region driven at a second driving frequency lower than the first driving frequency, (par 0064; discloses the display device 100 according to some example embodiments may perform multi-frequency driving (MFD) that drives a plurality of partial panel zones (or regions) PPZ1 and PPZ2 of the display panel 110 at a plurality of different driving frequencies DF1 and DF2; see par 0075 as well) wherein, in a first frame period, the controller generates the output enable signal having a first level during a first time within the first frame period allocated to the first panel region and a second time within the first frame period allocated to the second panel region such that the plurality of stages outputs output signals to both of the first panel region and the second panel region, (fig. 8; par 0055; discloses FIG. 8 is a diagram for describing an example of first and second driving frequencies determined for first and second partial panel zones of a display panel, and FIG. 9 is a timing diagram for describing an example of an operation of a display device according to some example embodiments; par 0062; discloses The scan driver 130 may provide the scan signals SS to the plurality of pixels PX through the plurality of scan lines based on a scan driver input signal SDIS received from the controller 140. In some example embodiments, the scan driver 130 may sequentially provide the scan signals SS to the plurality of pixels PX on a row-by-row basis) and wherein, in a second frame period, the controller generates the output enable signal having the first level during a third time within the second frame period allocated to the first panel region and a second level different from the first level during a fourth time within the second frame period allocated to the second panel region such that the plurality of stages outputs the output signals to the first panel region and does not output the output signals to the second panel region (par 0080; discloses the scan driver control block 180 may provide the scan output masking signal SOMS to the scan driver 130 in a partial period of the driving frame period assigned to a portion of the plurality of partial panel zones PPZ1 and PPZ2, so that the plurality of partial panel zones PPZ1 and PPZ2 may be driven at the plurality of different driving frequencies DF1 and DF2, or so that the scan signals SS may not be provided to the portion (e.g., a partial panel zone driven at a frequency lower than the maximum driving frequency of the plurality of driving frequencies DF1 and DF2) of the plurality of partial panel zones PPZ1 and PPZ2 within at least one driving frame period);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by YANG as modified by Zou and BYUN to incorporate the teachings of PARK to drive the different regions of panel at different frequencies and doesn’t output scan lines during partial period in order to reduce the power consumption of the display device.
Allowable Subject Matter
Claims 14, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 14, YANG alone or in view of other prior art of record fails to disclose wherein the PMOS boosting buffer includes: a boosting capacitor including a first electrode connected to a carry node at which the carry signal is output, and a second electrode connected to a fourth node; a seventh PMOS transistor including a gate connected to a line which transfers the low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node; and an eighth PMOS transistor including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to the line which transfers the low gate voltage; Hence claim 14 comprises allowable subject matter.
With respect to claim 18, YANG alone or in view of other prior art of record fails to disclose wherein the at least one stage further comprises: a boosting capacitor including a first electrode connected to the carry node, and a second electrode connected to a fourth node; a seventh PMOS transistor including a gate connected to the line which transfers the low gate voltage, a first terminal connected to the first node, and a second terminal connected to the fourth node; and an eighth PMOS transistor including a gate connected to the fourth node, a first terminal connected to the third node, and a second terminal connected to the line which transfers the low gate voltage, Hence claim 18 comprises allowable subject matter.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 17 and 19 have been considered but are moot because the new the argument do not apply to new reference being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUJIT SHAH whose telephone number is (571)272-5303. The examiner can normally be reached Monday-Friday, 9:00 am-6:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at (571)270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUJIT SHAH/Examiner, Art Unit 2624