DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Claims 21 – 40 are pending.
Response to Arguments
Applicant's arguments filed 15 June 2025 have been fully considered but they are not persuasive.
Applicant argues that the cited prior art, specifically US Patent No. 7,174,411 (hereinafter Ngai) in combination with US Patent Application Publication No.2009/0004920 (hereinafter Hulbert) and US Patent No. 7,886,103 (hereinafter Nishtala), does not teach the invention recited in at least claim 21. Specifically, Applicant argues that the cited references fail to teach a memory control integrated circuit. However, the Examiner respectfully disagrees. Hulbert shows that memory devices can be connected to a PCIe bus through a socket (Hulbert; Figure 7, Paragraph [0045]). Therefore, the Examiner asserts that, using a broadest reasonable interpretation of the claim language, PCIe circuitry can be considered "memory control integrated circuitry," as Hulbert shows that PCIe circuitry can be used to communicate with a memory device. Applicant has not defined the term "memory control integrated circuitry" in the specification or limited the term in the claims in such a way that would exclude the Examiner's interpretation of the claimed term. Therefore, the Examiner maintains that the prior art of record teaches every limitation of the claimed invention.
Applicant also argues that the cited prior art fails to teach splitting internal data conductors in response to a determination that a memory module socked is populated, as required by at least independent claim 21. However, the Examiner respectfully disagrees. Ngai teaches that lane configuration can be performed when a peripheral is inserted into a slot (Ngai; Col 3 Lines 33 - 38). Additionally, Nishtala teaches determining the presence of a memory module in a memory socket by reading configuration information of present modules to configure signal lines using a switch (Nishtala; Col 5 Line 63 - Col 6 Line 6). Therefore, the Examiner maintains that the combination of the prior art shows that signal configuration is performed when a peripheral is inserted into a slot (Ngai; Col 3 Lines 33 - 38) and when configuration information is read from a module in the slot (Nishtala; Col 5 Line 63 - Col 6 Line 6), which the Examiner equates to the claimed determination that the slot is populated. Therefore, the Examiner maintains the prior art of record teaches all the limitations of the claimed invention.
Applicant presents the same arguments for independent claims 31 and 40 as those presented with respect to independent claim 21. Therefore, the Examiner maintains that the prior art of record teaches all the limitations of independent claims 31 and 40 because of the reasons set forth above with respect to independent claim 21.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 26, 31, 36, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 13 (see mapping below) of U.S. Patent No. 11,200,181. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent require all the limitations of the claims of the instant application.
Instant Application
11,200,181
21
3
26
3
31
13
36
13
40
13
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 – 24, 31 – 34, and 40 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over US Patent No. 7,174,411 (hereinafter Ngai) in view of US Patent Application Publication No. 2009/0004920 (hereinafter Hubert), and further in view of US Patent No. 7,886,103 (hereinafter Nishtala).
As per claim 21, Ngai teaches a method of operation within an integrated circuit (IC) (Ngai; Col 8 Lines 10 – 13) having internal data conductors (Ngai; Figure 5 Items 20A – 20P) and distinct first (Ngai; Figure 5 Item 30 – 16 lane interface which connects the SLOT1 PERIPH 30 to the lanes) and second data interfaces (Ngai; Figure 5 Item 32 – 8 lane interface which connects the SLOT2 PERIPH 32 to the lanes) to be coupled, respectively to first (Ngai; Figure 5 Item 30) and second (Ngai; Figure 5 Item 32) sockets, the first data interface being twice as wide as the second data interface (Ngai; Figure 5 – “16 LANES” and “8 LANES”), the method comprising: splitting connection of the internal data conductors between the first and second data interfaces in response to determining that the second socket is populated (See “Response to Arguments” presented above), including switchably coupling (Ngai; Figure 5 Items 40A – 40H) a first half of the internal data conductors (Ngai; Figure 5 Items 20I – 20P) to the second data interface while a second half of the internal data conductors (Ngai; Figure 5 Items 20A – 20H) remain coupled to the first data interface.
Ngai does not teach wherein the integrated circuit is a memory-control integrated circuit; the first and second sockets are memory module sockets; determining whether the second memory module socket is populated by a memory module having a nonvolatile storage component, including attempting to read configuration information from the nonvolatile memory component.
However, Hubert teaches a system in which a memory device (Hubert; Figure 7 Item 140) can be coupled to a PCIe bus through a socket (Hulbert; Figure 7, Paragraph [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the invention was made to have modified the teachings of Ngai to include the memory device because doing so is one of many different peripheral types which could be coupled to the system through the PCIe bus.
Ngai in combination with Hubert does not teach determining whether the second memory module socket is populated by a memory module having a nonvolatile storage component, including attempting to read configuration information from the nonvolatile memory component.
However, Nishtala teaches a system in which a presence of a memory module in a memory module socket is determined by reading configuration information from a nonvolatile memory component of the memory module (Nishtala; Col 2 Lines 48 – 60, Col 5 Line 63 – Col 6 Line 6) (See “Response to Arguments” presented above).
Therefore, it would have been obvious to one of ordinary skill in the art before the invention was made to have modified the teachings of Ngai in combination with Hubert to include determining whether the socket is populated by reading the configuration information because doing so allows for determining peripheral capabilities (Nishtala; Col 5 Line 63 – Col 6 Line 6).
As per claims 22 and 32, Ngai also teaches wherein splitting connection of the internal data conductors between the first and second data interfaces further comprises switchably decoupling the first half the internal data conductors from the first data interface (Ngai; Figure 5 Items 40A – 40H).
As per claims 23 and 33, Ngai also teaches wherein a first portion of the internal data conductors are permanently coupled to the first data interface (Ngai; Figure 5 Items 20A – 20H) and a second portion of the internal data conductors, including at least the first half of the internal data conductors (Ngai; Figure 5 Items 20I – 20P) are coupled to switching circuitry (Ngai; Figure 5 Items 40A – 40H) within the memory-control IC, the switching circuitry enabling the first half of the internal data conductors to be switchably coupled exclusively to either the second data interface or the first data interface (Ngai; Figure 5).
As per claims 24 and 34, Ngai also teaches wherein the first portion of the internal data conductors constitute at least some of the internal data conductors within the second half of the internal data conductors (Ngai; Figure 5 Items 20A – 20H).
As per claim 31, Ngai teaches an integrated-circuit (Ngai; Col 8 Lines 10 – 13) comprising: internal data conductors (Ngai; Figure 5 Items 20A – 20P); a first data interface (Ngai; Figure 5 Item 30 – 16 lane interface which connects the SLOT1 PERIPH 30 to the lanes) to be coupled to a first socket (Ngai; Figure 5 Item 30); a second data interface (Ngai; Figure 5 Item 32 – 8 lane interface which connects the SLOT2 PERIPH 32 to the lanes), not more than half as wide as the first data interface (Ngai; Figure 5 – “16 LANES” and “8 LANES”), to be coupled to a second socket (Ngai; Figure 5 Item 32); and switching circuitry (Ngai; Figure 5 Items 40A – 40H) to split connection of the internal data conductors between the first and second data interfaces in response to determining that the second socket is populated (See “Response to Arguments” presented above), including circuitry to switchably couple (Ngai; Figure 5 Items 40A – 40H) a first half of the internal data conductors (Ngai; Figure 5 Items 20I – 20P) to the second data interface while a second half of the internal data conductors (Ngai; Figure 5 Items 20A – 20H) remain coupled to the first data interface.
Ngai does not teach wherein the integrated circuit is a memory control integrated circuit; the first and second sockets are memory module sockets; and control circuitry to determine whether the second memory module socket is populated by a memory module having a nonvolatile storage component at least in part by attempting to read configuration information from the nonvolatile memory component.
However, Hubert teaches a system in which a memory device (Hubert; Figure 7 Item 140) can be coupled to a PCIe bus through a socket (Hulbert; Figure 7, Paragraph [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the invention was made to have modified the teachings of Ngai to include the memory device because doing so is one of many different peripheral types which could be coupled to the system through the PCIe bus.
Ngai in combination with Hubert does not teach determining whether the second memory module socket is populated by a memory module having a nonvolatile storage component, including attempting to read configuration information from the nonvolatile memory component.
However, Nishtala teaches a system in which a presence of a memory module in a memory module socket is determined by reading configuration information from a nonvolatile memory component of the memory module (Nishtala; Col 2 Lines 48 – 60, Col 5 Line 63 – Col 6 Line 6) (See “Response to Arguments” presented above).
Therefore, it would have been obvious to one of ordinary skill in the art before the invention was made to have modified the teachings of Ngai in combination with Hubert to include determining whether the socket is populated by reading the configuration information because doing so allows for determining peripheral capabilities (Nishtala; Col 5 Line 63 – Col 6 Line 6).
As per claim 40, Ngai teaches an integrated-circuit (Ngai; Col 8 Lines 10 – 13) comprising: internal data conductors (Ngai; Figure 5 Items 20A – 20P); a first data interface (Ngai; Figure 5 Item 30 – 16 lane interface which connects the SLOT1 PERIPH 30 to the lanes) to be coupled to a first socket (Ngai; Figure 5 Item 30); a second data interface (Ngai; Figure 5 Item 32 – 8 lane interface which connects the SLOT2 PERIPH 32 to the lanes), not more than half as wide as the first data interface (Ngai; Figure 5 – “16 LANES” and “8 LANES”), to be coupled to a second socket (Ngai; Figure 5 Item 32); and means for: splitting connection of the internal data conductors between the first and second data interfaces in response to determining that the second socket is populated (See “Response to Arguments” presented above), including switchably coupling (Ngai; Figure 5 Items 40A – 40H) a first half of the internal data conductors (Ngai; Figure 5 Items 20I – 20P) to the second data interface while a second half of the internal data conductors (Ngai; Figure 5 Items 20A – 20H) remain coupled to the first data interface.
Ngai does not teach wherein the integrated circuit is a memory-control integrated circuit; the first and second sockets are memory module sockets; determining whether the second memory module socket is populated by a memory module having a nonvolatile storage component, including means for attempting to read configuration information from the nonvolatile memory component.
However, Hubert teaches a system in which a memory device (Hubert; Figure 7 Item 140) can be coupled to a PCIe bus through a socket (Hulbert; Figure 7, Paragraph [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the invention was made to have modified the teachings of Ngai to include the memory device because doing so is one of many different peripheral types which could be coupled to the system through the PCIe bus.
Ngai in combination with Hubert does not teach determining whether the second memory module socket is populated by a memory module having a nonvolatile storage component, including attempting to read configuration information from the nonvolatile memory component.
However, Nishtala teaches a system in which a presence of a memory module in a memory module socket is determined by reading configuration information from a nonvolatile memory component of the memory module (Nishtala; Col 2 Lines 48 – 60, Col 5 Line 63 – Col 6 Line 6) (See “Response to Arguments” presented above).
Therefore, it would have been obvious to one of ordinary skill in the art before the invention was made to have modified the teachings of Ngai in combination with Hubert to include determining whether the socket is populated by reading the configuration information because doing so allows for determining peripheral capabilities (Nishtala; Col 5 Line 63 – Col 6 Line 6).
Allowable Subject Matter
Claims 25 – 30 and 35 – 39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 25 and 35 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination programming memory ICs mounted to a memory module within the first memory module socket to have a collective data interface width that matches the width of the first data interface in response to determining that the second memory module socket is not populated by the memory module having the nonvolatile storage component, as required by dependent claims 25 and 35, in combination with the other claimed limitations (emphasis added). The prior art of record teaches switching the width of a data interface connected to a memory module socket, but does not teach the step of programming the memory ICs mounted to the memory module within the memory module socket as required by dependent claims 25 and 35.
Claims 26 – 30 and 36 – 39 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination programming memory ICs mounted to a memory module within the first memory module socket to have a collective data interface width half that of the first data interface in response to determining that the second memory module socket is populated by the memory module having the nonvolatile storage component, as required by dependent claims 26 and 36, in combination with the other claimed limitations (emphasis added). The prior art of record teaches switching the width of a data interface connected to a memory module socket, but does not teach the step of programming the memory ICs mounted to the memory module within the memory module socket as required by dependent claims 26 and 36.
Claims 27 – 30 and 37 – 39 would also be allowable because of their dependence, either directly or indirectly, upon one of allowable dependent claims 26 or 36.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181
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