DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities:
In the last line of claim 20, please remove the comma (,) before the period (.) ending the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 15 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kwak (US Pat Pub 2022/0165346).
Regarding claim 1, Kwak discloses a semiconductor memory device comprising:
a plurality of memory cells (para 0040, “internal circuit 160 may include a plurality of memory cells”);
a plurality of peripheral circuits configured to perform a write operation comprising storing write data transmitted from a memory controller into the plurality of memory cells and a read operation comprising reading out read data of data stored in the plurality of memory cells to transfer the read data to the memory controller (para 0040, referred to as the “logic blocks for accessing the memory cells”. “The internal circuit 160 may output read data DQ from the memory cells … during read operation”; “The internal circuit 160 may perform an internal operation such as the write operation… by setting the operational mode according to the setting codes… provided from the register sets…”. See also para 0038, 0040, etc…); and
a mode controller (referred to as the mode register circuit 140, para 0033) configured to receive mode information from the memory controller (referred to as the mode decoder 130, para 0031), and, based on the mode information from the memory controller (130), control the plurality of peripheral circuits to operate in one of a normal mode for performing both the write operation and the read operation (see para 0038, read/write mode, normal operation by reading out the pre-stored codes), a read-only mode for performing the read operation without performing the write operation, or a write-only mode for performing the write operation without performing the read operation (see para 0004, 0034, 0035).
Regarding claim 2, Kwak also discloses the semiconductor memory device of claim 1, wherein the plurality of peripheral circuits comprises mode registers (see abstract) configured to store control values for controlling operations of the semiconductor memory device (see para 0004, 0030, mode register command), and wherein the semiconductor memory device is configured to receive the mode information through a mode register write command transmitted from the memory controller and is configured to store the mode information in a first mode register of the mode registers (referred to as the storing circuit 210, para 0043. See also para 0030 – 0049).
As per claim 15, Kwak also discloses the semiconductor memory device of claim 1, wherein the plurality of memory cells correspond to DRAM cells and the semiconductor memory device corresponds to a DRAM device (see para 0003 – 0004).
Allowable Subject Matter
Claims 19 and 20 are allowed.
Claims 3, 4 – 9, 16 – 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest a memory system as set forth in claim 19, comprising in combination: a semiconductor memory device; and a memory controller configured to control the semiconductor memory device, wherein the semiconductor memory device comprises: a plurality of memory cells; a plurality of peripheral circuits configured to perform a write operation comprising storing write data transmitted from the memory controller into the plurality of memory cells and a read operation comprising reading out read data of data stored in the plurality of memory cells to transfer the read data to the memory controller; and a mode controller configured to receive mode information from the memory controller, and, based on the mode information from the memory controller, control the plurality of peripheral circuits to operate in one of a normal mode for performing both the write operation and the read operation, a read-only mode for performing the read operation without performing the write operation, or a write-only mode for performing the write operation without performing the read operation, and wherein the memory controller is configured to provide the semiconductor memory device with the mode information indicating one of the normal mode, the read-only mode or the write-only mode, based on an access type with respect to the semiconductor memory device.
The prior arts of record also fail to teach or reasonably suggest a semiconductor memory device as set forth in claim 20, comprising in combination: a plurality of dynamic random access memory (DRAM) cells; read-only circuits that are used for a read operation comprising reading out read data of data stored in the plurality of DRAM cells to transfer the read data to a memory controller and are not used for a write operation comprising storing write data transmitted from the memory controller into the plurality of DRAM cells; write-only circuits that are used for the write operation and are not used for the read operation; and a mode controller configured to receive mode information from the memory controller, and, based on the mode information from the memory controller, enable both the read-only circuits and the write-only circuits in a normal mode that performs both the write operation and the read operation, disable the write-only circuits in a read-only mode that performs the read operation without performing the write operation, or disable the read-only circuits in a write-only mode that performs the write operation without performing the read operation.
The prior arts of record further fail to teach or reasonably suggest, the semiconductor memory device as set forth in claim 1 above, further comprising, in combination, the features and limitations additionally claimed at least in claims 3, 4, 8, 9 and 16 – 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 June 3, 2026
Prosecution Insights