DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choy et al. (Patent 9741435), hereinafter as Choy.
Regarding claim 1, Choy teaches an apparatus, comprising:
a memory array comprising memory cells (Fig 1, cells);
sensing circuitry coupled to the memory array and configured to: apply, using a first transistor (Fig 6, 249) and a capacitor (Fig 6, 235) of a current mirror (Fig 6), a first signal to a terminal of a particular transistor (Fig 6, 251);
mirror the first signal to circuitry using a second transistor (Fig 6, 233) and the capacitor of the current mirror;
apply a second signal to a gate (Fig 6, the gate of 251) of the particular transistor, the second signal comprising a signal drop on the circuitry (Fig 6 , node 207, has voltage drops related to 211 and 109); and sense a state of the particular transistor (Fig 6).
Regarding claim 2, Choy teaches the first transistor is configured to receive a supply voltage at a first terminal and the second transistor is configured to receive the supply voltage at a second terminal (Fig 6 VDD1).
Regarding claim 3, Choy teaches the first transistor is configured to provide the first signal from a third terminal of the first transistor based on a different signal provided to a first gate of the first transistor by the capacitor (Fig 6, when switches 237 and 245 at connecting states).
Regarding claim 4, Choy teaches the second transistor is configured to mirror the first signal by providing a second signal from a fourth terminal of the second transistor based on the different signal provided to second gate of the second transistor by the capacitor (Fig 6).
Note: claim 5-6 and 7/17 are rejected based on DP only.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11508455/12176052. Although the claims at issue are not identical, they are not patentably distinct from each other because at least the independent claim 1/7/17 is rejected by the claims of 11508455/12176052, as matching listed below in a table.
Instant app
11508455(as ‘5), 12176052(as ‘2)
PNG
media_image1.png
462
914
media_image1.png
Greyscale
’5 (claim 6-9)
PNG
media_image2.png
810
408
media_image2.png
Greyscale
’2
PNG
media_image3.png
380
896
media_image3.png
Greyscale
PNG
media_image4.png
630
666
media_image4.png
Greyscale
‘2
PNG
media_image5.png
492
398
media_image5.png
Greyscale
PNG
media_image6.png
410
678
media_image6.png
Greyscale
‘5
PNG
media_image7.png
622
926
media_image7.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/Primary Examiner, Art Unit 2827
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