DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed November 26, 2024.
Claims 1-20 are pending. Claims 1, 10 and 17 are independent.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 14, 2025. This IDS has been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (U.S. 9,911,847; hereinafter “Chin”) in view of Gong et al. (U.S. 2022/0208259; hereinafter “Gong”).
Regarding independent claim 1, Chin teaches a capacitor device (Fig. 7) comprising:
first conductive layer providing a first capacitor terminal (Fig. 7: CG) and a second conductive layer providing a second capacitor terminal (Fig. 7: 10) and an insulating dielectric material layer therebetween (Fig. 7: 21-24), said first conductive layer, second conductive layer and insulating dielectric material layer forming a stack (Fig. 7);
a floating gate semiconductor material layer disposed within the insulating material layer and configured for storing charge carriers (Fig. 7: 22);
a first dielectric material layer formed along a sidewall of said stack and contacting a side edge of said floating gate semiconductor material layer (Fig. 7: SP2(31));
a second dielectric material layer formed along an opposing sidewall of said stack and contacting an opposite side edge of said floating gate semiconductor material layer (Fig. 7: SP1(31));
a first conductive electrode providing a third capacitor terminal separated from the side edge of the floating gate semiconductor material layer by the first dielectric material layer (Fig. 7: SG), and
a second conductive electrode providing a fourth capacitor terminal separated from the opposite side edge of the floating gate semiconductor material layer by the second dielectric material layer (Fig. 7: EG).
However, Chin is silent with respect to said capacitor device associated with a weight update circuit at a crossbar array node of a neural network circuit, a capacitance of said capacitor device taken across said first and second capacitor terminal representing a weight value used in a neural network circuit operation.
Similar to Chin, Gong teaches a capacitor device (see Abstract) comprising multiple terminals (see Fig. 3).
Furthermore, Gong teaches said capacitor device associated with a weight update circuit (Fig. 3: 795) at a crossbar array node (Fig. 3) of a neural network circuit (see page 2, par. 0025), a capacitance of said capacitor device taken across said first and second capacitor terminal representing a weight value used in a neural network circuit operation (see pages 2-3, par. 0025-0026).
Since Gong and Chin are from the same field of endeavor, the teachings described by Gong would have been recognized in the pertinent art of Chin.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Gong with the teachings of Chin for the purpose of provide electronic circuitry suitable for implementing neural networks, see Gong’s page 1, par. 0001.
Regarding independent claim 10, Chin teaches a circuit comprising:
a capacitor device (Fig. 7) comprising:
first conductive layer providing a first capacitor terminal (Fig. 7: CG) and a second conductive layer providing a second capacitor terminal (Fig. 7: 10) and an insulating dielectric material layer therebetween (Fig. 7: 21-24), said first conductive layer, second conductive layer and insulating dielectric material layer forming a stack (Fig. 7);
a floating gate semiconductor material layer disposed within the insulating material layer and configured for storing charge carriers (Fig. 7: 22);
a first dielectric material layer formed along a sidewall of said stack and contacting a side edge of said floating gate semiconductor material layer (Fig. 7: SP2(31));
a second dielectric material layer formed along an opposing sidewall of said stack and contacting an opposite side edge of said floating gate semiconductor material layer (Fig. 7: SP1(31));
a first conductive electrode providing a third capacitor terminal separated from the side edge of the floating gate semiconductor material layer by the first dielectric material layer (Fig. 7: SG), and
a second conductive electrode providing a fourth capacitor terminal separated from the opposite side edge of the floating gate semiconductor material layer by the second dielectric material layer (Fig. 7: EG).
However, Chin is silent with respect to a neural network circuit comprising a crossbar array comprising a plurality of nodes; each node comprising a capacitive processing unit (CPU) including a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation and said capacitor device associated with a weight update circuit at a crossbar array node of a neural network circuit, a capacitance of said capacitor device taken across said first and second capacitor terminals representing a weight value used in a neural network circuit operation.
Similar to Chin, Gong teaches a capacitor device (see Abstract).
Furthermore, Gong teaches a neural network circuit (see page 2, par. 0025) comprising a crossbar array comprising a plurality of nodes (Fig. 3); each node comprising a capacitive processing unit (CPU) including a capacitor device configured to store a charge representing a weight value associated with a neural network circuit operation (Fig. 3 shows charge capacitors in a crossbar array) and said capacitor device associated with a weight update circuit (Fig. 3: 795) at a crossbar array node (Fig. 3) of a neural network circuit (see page 2, par. 0025), a capacitance of said capacitor device taken across said first and second capacitor terminal representing a weight value used in a neural network circuit operation (see pages 2-3, par. 0025-0026).
Since Gong and Chin are from the same field of endeavor, the teachings described by Gong would have been recognized in the pertinent art of Chin.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Gong with the teachings of Chin for the purpose of provide electronic circuitry suitable for implementing neural networks, see Gong’s page 1, par. 0001.
Claims 2-8, 11-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chin and Gong as applied to claim 1 above, and further in view of Hekmatshoartabari et al. (U.S. 2022/0108997; hereinafter “Hekmatshoartabari”).
Regarding claim 2, Chin in combination with Gong teaches the limitations with respect to claim 1.
Furthermore, Chin teaches wherein said third capacitor terminal and said fourth capacitor terminal are adapted to receive signals for updating an amount of charge carriers stored at said floating gate semiconductor material layer to modify a capacitance of said capacitor device (see col. 5, ll. 11-36).
However, the combination is silent with respect to wherein said first dielectric material layer formed along a sidewall of said stack comprises a first horizontal dielectric material layer portion extending on a top surface of said first semiconductor material layer on one side of said stack, and the second dielectric material layer formed on an opposing sidewall of said stack comprises a second horizontal layer portion extending on a top surface of said first semiconductor material layer on another side of said stack, wherein the first conductive electrode is formed on said horizontal dielectric material layer portion and abutting the first dielectric material layer formed on the sidewall of said stack; and the second conductive electrode formed on said second dielectric material layer and abutting the second dielectric material layer formed on the opposing sidewall of said stack.
Similar to the combination, Hekmatshoartabari teaches a stacked device comprising floating gate semiconductor material layer (see Fig. 10).
Furthermore, Hekmatshoartabari teaches first dielectric material layer formed along a sidewall of said stack comprises a first horizontal dielectric material layer portion extending on a top surface of said first semiconductor material layer on one side of said stack (Fig. 10: 128 and 134 on left side), and the second dielectric material layer formed on an opposing sidewall of said stack comprises a second horizontal layer portion extending on a top surface of said first semiconductor material layer on another side of said stack (Fig. 10: 128 and 134 on right side),
wherein the first conductive electrode is formed on said horizontal dielectric material layer portion and abutting the first dielectric material layer formed on the sidewall of said stack (Fig. 10: 136); and
the second conductive electrode formed on said second dielectric material layer and abutting the second dielectric material layer formed on the opposing sidewall of said stack (Fig. 10: 138).
Since Hekmatshoartabari, Gong and Chin are from the same field of endeavor, the teachings described by Hekmatshoartabari would have been recognized in the pertinent art of Chin in combination with Gong.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hekmatshoartabari with the teachings of Chin in combination with Gong for the purpose of provide a low voltage memory device, see Hekmatshoartabari’s Abstract.
Regarding claim 3, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 2.
Furthermore, Hekmatshoartabari teaches wherein said first conductive electrode comprises a low work function metal material (Fig. 10: portion 136 can comprise a conductive material such as Aluminum (Al) which has a lower work function than Titanium (Ti), see page 5, par. 0059), and said second conductive electrode comprises a high work function metal material (Fig. 10: portion 138 can comprise a conductive material such as Titanium (Ti) which has a higher work function than Aluminum (Al), see page 6, par. 0065).
Regarding claim 4, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 3.
Furthermore, Hekmatshoartabari teaches wherein said first dielectric material layer and second dielectric material layer are of substantially identical thickness (Fig. 10 shows elements 134 having substantially identical thickness).
Regarding claim 5, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 3.
Furthermore, Hekmatshoartabari teaches wherein one of said first dielectric material layer and second dielectric material layer comprises an oxide material of a thickness permitting tunneling of charge carriers therethrough for incrementing or decrementing an amount of charge carriers stored in said floating gate semiconductor material layer (see pages 4-5 , par. 0050-0051).
Regarding claim 6, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 5.
Furthermore, Hekmatshoartabari teaches wherein both said first conductive electrode and second conductive electrode comprise a low work function metal material (Fig. 10: portion 136 and 138 can comprise a conductive material such as Aluminum (Al) which has a lower work function, see page 5, par. 0059 and page 6, par. 0065).
Regarding claim 7, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 6.
Furthermore, Hekmatshoartabari teaches wherein said second dielectric material layer is of a thickness greater than a thickness of said first dielectric material layer (The thickness of 134 may vary with respect to 128, see pages 4-5, par. 0051 and 0058).
Regarding claim 8, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 2.
Furthermore, Gong teaches said capacitor device associated is connected to a weight update circuit (Fig. 3: 795) at a crossbar array node (Fig. 3) of a neural network circuit adapted to conduct neural network operations (see page 2, par. 0025), a capacitance of said capacitor device representing a weight value used in a neural network circuit operation (see pages 2-3, par. 0025-0026).
Regarding claim 11, Chin in combination with Gong teaches the limitations with respect to claim 10.
Furthermore, Chin teaches wherein said third capacitor terminal and said fourth capacitor terminal are adapted to receive signals for updating an amount of charge carriers stored at said floating gate semiconductor material layer to modify a capacitance of said capacitor device (see col. 5, ll. 11-36).
However, the combination is silent with respect to wherein said first dielectric material layer formed along a sidewall of said stack comprises a first horizontal dielectric material layer portion extending on a top surface of said first semiconductor material layer on one side of said stack, and the second dielectric material layer formed on an opposing sidewall of said stack comprises a second horizontal layer portion extending on a top surface of said first semiconductor material layer on another side of said stack, wherein the first conductive electrode is formed on said horizontal dielectric material layer portion and abutting the first dielectric material layer formed on the sidewall of said stack; and the second conductive electrode formed on said second dielectric material layer and abutting the second dielectric material layer formed on the opposing sidewall of said stack.
Similar to the combination, Hekmatshoartabari teaches a stacked device comprising floating gate semiconductor material layer (see Fig. 10).
Furthermore, Hekmatshoartabari teaches first dielectric material layer formed along a sidewall of said stack comprises a first horizontal dielectric material layer portion extending on a top surface of said first semiconductor material layer on one side of said stack (Fig. 10: 128 and 134 on left side), and the second dielectric material layer formed on an opposing sidewall of said stack comprises a second horizontal layer portion extending on a top surface of said first semiconductor material layer on another side of said stack (Fig. 10: 128 and 134 on right side),
wherein the first conductive electrode is formed on said horizontal dielectric material layer portion and abutting the first dielectric material layer formed on the sidewall of said stack (Fig. 10: 136); and
the second conductive electrode formed on said second dielectric material layer and abutting the second dielectric material layer formed on the opposing sidewall of said stack (Fig. 10: 138).
Since Hekmatshoartabari, Gong and Chin are from the same field of endeavor, the teachings described by Hekmatshoartabari would have been recognized in the pertinent art of Chin in combination with Gong.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Hekmatshoartabari with the teachings of Chin in combination with Gong for the purpose of provide a low voltage memory device, see Hekmatshoartabari’s Abstract.
Regarding claim 12, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 11.
Furthermore, Gong teaches wherein the CPU at a crossbar array node of the neural network circuit comprises:
a first Field Effect Transistor (FET) device operatively connecting a first conductor line to said first capacitor terminal and adapted to conduct a signal from a voltage source to charge said capacitor device for use in a matrix vector multiplication neural network operation (Fig. 3: 705 connecting 701 to capacitor 709); and
a second FET device operatively connecting a second conductor line to said second capacitor terminal and adapted to conduct a signal representing said charge stored at said capacitor device to a charge integrator device for use in said matrix vector multiplication neural network circuit operation (Fig. 3: 707 connecting 703 to capacitor 709).
Regarding claim 14, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 11.
Furthermore, Hekmatshoartabari teaches wherein said first conductive electrode comprises a low work function metal material (Fig. 10: portion 136 can comprise a conductive material such as Aluminum (Al) which has a lower work function than Titanium (Ti), see page 5, par. 0059), and said second conductive electrode comprises a high work function metal material (Fig. 10: portion 138 can comprise a conductive material such as Titanium (Ti) which has a higher work function than Aluminum (Al), see page 6, par. 0065), said first dielectric material layer and second dielectric material layer being of substantially identical thickness (Fig. 10 shows elements 134 having substantially identical thickness).
Regarding claim 15, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 11.
Furthermore, Hekmatshoartabari teaches wherein one of said first dielectric material layer and second dielectric material layer comprises an oxide material of a thickness permitting tunneling of charge carriers therethrough for incrementing or decrementing an amount of charge carriers stored in said floating gate semiconductor material layer (see pages 4-5 , par. 0050-0051).
Regarding claim 16, Chin in combination with Gong and Hekmatshoartabari teaches the limitations with respect to claim 11.
Furthermore, Hekmatshoartabari teaches wherein both said first conductive electrode and second conductive electrode comprise a low work function metal material (Fig. 10: portion 136 and 138 can comprise a conductive material such as Aluminum (Al) which has a lower work function, see page 5, par. 0059 and page 6, par. 0065), said second dielectric material layer is of a thickness greater than a thickness of said first dielectric material layer (The thickness of 134 may vary with respect to 128, see pages 4-5, par. 0051 and 0058).
Allowable Subject Matter
Claims 9 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 9, there is no teaching or suggestion in the prior art of record to provide the recited weight update circuit at the crossbar array node of the neural network circuit comprises: a first conductor structure operatively connected to said third capacitor terminal and adapted to conduct a first pulsed signal from a signal generator to said third capacitor terminal; and a second conductor structure operatively connected to said fourth capacitor terminal and adapted to conduct a second pulsed signal from the signal generator to said fourth capacitor terminal, said first pulsed signal and second pulsed signals used to update said capacitance of said capacitor device during an outer-product update neural network circuit operation.
With respect to claim 13, there is no teaching or suggestion in the prior art of record to provide the recited CPU comprises a weight update circuit at the crossbar array node of the neural network circuit, said weight update circuit comprising: a third conductor line operatively connected to said third capacitor terminal and adapted to conduct a first pulsed signal from a signal generator to said third capacitor terminal; and a fourth conductor line operatively connected to said fourth capacitor terminal and adapted to conduct a second pulsed signal from the signal generator to said fourth capacitor terminal, said first pulsed signal and second pulsed signals used to update said capacitance of said capacitor device during an outer-product update neural network circuit operation.
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 17, there is no teaching or suggestion in the prior art of record to provide the recited step of programming the weight value of said weight update circuit for said neural network circuit operation by modifying a capacitance of the capacitor device associated with said weight update circuit using both the third and fourth capacitor terminals, in combination with the other limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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