DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 11/26/2024. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 18960776 filed 11/26/2024 is a Continuation of 18128725, filed 03/30/2023, now U.S. Patent No. 12,199,641.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claims 1, 8 and 15 recite an abstract idea directed to a group of mathematical concepts, under Step 2A Prong 1, according to the limitations:
receiving, by a device, a downlink signal from a base station;
generating, by the device, a mapping matrix for mapping a scrambling sequence initialization to frozen bits from data of the downlink signal;
determining, by the device, an inverse matrix of the mapping matrix;
obtaining, by the device and based on the inverse matrix and the frozen bits, a final matrix;
recovering, by the device and based on the final matrix, scrambling sequence seed bits; and
performing, by the device, one or more actions without performing a descrambling operation.
The limitations recited in the Claims, which as drafted, are directed to a group of mathematical concepts. According to the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), under their broadest reasonable interpretation, the limitations cover performance of mathematical concepts, such as, mathematical relationships, mathematical formulas or equations, and mathematical calculations.
If a claim limitation, under its broadest reasonable interpretation, covers performance of mathematical calculations, such as in this case, the limitations as recited in independent Claims 1, 8 and 15, then it falls within the “Mathematical Concepts” of abstract ideas.
For example, in Claims 1, 8 and 15, the limitation “generating a mapping matrix for mapping a scrambling sequence initialization to frozen bits” is expressed by a series of mathematical expressions for calculating the scrambling sequence denoted by c∈F2E, as described in the specification para. [0013].
Also, the limitation “obtaining, by the device and based on the inverse matrix and the frozen bits, a final matrix” is also expressed by a series of mathematical equations in para. [0027] of the specification. The testing system may determine the inverse matrix (Z~) as follows: Z~=ZC~, (18) ], which falls within the “Mathematical Concepts” of abstract ideas.
For example, the limitation in Claims 1, 8 and 15, “recovering, by the device and based on the final matrix, scrambling sequence seed bits” is expressed by a series of mathematical equations. The testing system may recover seed bits (cinit) from the data (b) of the downlink signal based on the following calculation: cinit=b~X2MATRIX+x1mask(1), See, para. [0022] of the specification.
Accordingly, the claims recite an abstract idea, and hence non-eligible subject matter under the 101 requirement.
This judicial exception is not integrated into a practical application under, Step 2A Prong 2. In particular, the claims recite additional elements, such as, one or more processors, coupled to the one or more memories are merely used as a generic tool. The additional element, such as a processor to execute instructions for performing mathematical calculations is nothing else than a general purpose computer being used as a generic tool. Thus it constitutes an abstract idea without any tangible results, and without further reciting any practical applications, for achieving such results.
Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Accordingly, the claims recite an abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, the additional elements amounts to no more than a processor to execute instructions cannot provide an inventive concept. Hence, the claims are not patent eligible under the 101 requirement.
The dependent Claims 2-7, 9-14 and 16-20 do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
For example, the additional elements recited in Claims 6, 13, 20, “obtaining the final matrix based on the inverse matrix and the first matrix” do not amount to significantly more than the judicial exception, because the multiplication used to calculate the final matrix, is a mathematical operation, that may be performed by a conventional computer used as a tool, as evident by the specification. Para. [0052] As shown in Fig. 4, process 400 may include multiplying the inverse matrix and the frozen decode matrix to obtain a final matrix (block 460). For example, the device may multiply the inverse matrix and the frozen decode matrix to obtain a final matrix.
Therefore, the Claims recite an abstract idea, and hence non-eligible subject matter under the 101 requirement.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,199,641. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,199,641, and thus anticipate the Claims of the instant Application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
TABLE A: Claims comparison
18960776 Instant Application Claims
(U.S. Patent No. 12,199,641) Claims
1. A method, comprising:
receiving, by a device, a downlink signal from a base station;
generating, by the device, a mapping matrix for mapping a scrambling sequence initialization to frozen bits from data of the downlink signal;
determining, by the device, an inverse matrix of the mapping matrix;
obtaining, by the device and based on the inverse matrix and the frozen bits, a final matrix;
recovering, by the device and based on the final matrix, scrambling sequence seed bits; and
performing, by the device, one or more actions without performing a descrambling operation.
1. A method, comprising:
receiving, by a device, a downlink signal from a base station;
constructing, by the device, a frozen decode matrix for decoding frozen bits from data of the downlink signal; constructing, by the device, a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits;
generating, by the device and based on the frozen decode matrix and the LFSR generator matrix, a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits; determining, by the device, an inverse matrix of the mapping matrix;
obtaining, by the device and based on the inverse matrix and the frozen decode matrix, a final matrix;
utilizing, by the device, the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits; and
decoding, by the device, the downlink signal based on the scrambling sequence seed bits.
8. A device, comprising:
one or more memories; and one or more processors, coupled to the one or more memories, configured to:
receive a downlink signal from a base station;
generate a mapping matrix for mapping a scrambling sequence initialization to frozen bits from data of the downlink signal;
determine an inverse matrix of the mapping matrix;
obtain, based on the inverse matrix and the frozen bits, a final matrix;
recover, based on the final matrix, scrambling sequence seed bits; and perform one or more actions without performing a descrambling operation.
8. A device, comprising: one or more memories; and one or more processors, coupled to the one or more memories, configured to:
receive a downlink signal from a base station, wherein the downlink signal includes one of:
a physical broadcast channel signal, or a physical downlink control channel signal; construct a frozen decode matrix for decoding frozen bits from data of the downlink signal;
construct a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits; generate, based on the frozen decode matrix and the LFSR generator matrix, a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits;
determine an inverse matrix of the mapping matrix;
obtain, based on the inverse matrix and the frozen decode matrix, a final matrix;
utilize the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits; and
perform, without performing a descrambling operation, one or more actions based on the scrambling sequence seed bits.
15. A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device, cause the device to:
receive a downlink signal from a base station;
generate a mapping matrix for mapping a scrambling sequence initialization to frozen bits from data of the downlink signal;
determine an inverse matrix of the mapping matrix;
obtain, based on the inverse matrix and the frozen bits, a final matrix;
recover, based on the final matrix, scrambling sequence seed bits; and
perform one or more actions without performing a descrambling operation.
15. A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device, cause the device to:
receive a downlink signal from a base station, wherein the downlink signal is a New Radio downlink control signal; construct a frozen decode matrix for decoding frozen bits from data of the downlink signal;
construct a linear feedback shift register (LFSR) generator matrix for a component of scrambling sequence seed bits; generate, based on the frozen decode matrix and the LFSR generator matrix, a mapping matrix for mapping a value of a scrambling sequence initialization vector that initializes a scrambler to the frozen bits;
determine an inverse matrix of the mapping matrix;
obtain, based on the inverse matrix and the frozen decode matrix, a final matrix; utilize the final matrix to recover, from the data of the downlink signal, the scrambling sequence seed bits; and perform, without performing a descrambling operation, one or more actions based on the scrambling sequence seed bits.
2, 3, 9, 10, 16, 17. wherein the downlink signal comprises an uncoded downlink channel information (DCI) vector, and
wherein the downlink signal includes a signal on a physical channel that carries downlink channel information (DCI).
2, 3. wherein the downlink signal includes a physical downlink control channel signal, and wherein the downlink signal includes uncoded downlink control information.
4, 11, 18.constructing a first matrix associated with the frozen bits from data of the downlink signal; and constructing a second matrix associated with a component of the scrambling sequence seed bits, wherein the mapping matrix is based on the first matrix and the second matrix.
4, 16. wherein constructing the frozen decode matrix for decoding the frozen bits from the data of the downlink signal comprises: determining an input-output relation of polar encoding based on the downlink signal; performing an interleaving operation with the input-output relation to obtain an interleaved vector; and utilizing rate matching with the interleaved vector to construct the frozen decode matrix.
5, 12, 19. determining an input-output relation of polar encoding based on the downlink signal; obtaining an interleaved vector based on the input-out relation; and constructing the first matrix based on rate matching with the interleaved vector.
16. determine an input-output relation of polar encoding based on the downlink signal; perform an interleaving operation with the input-output relation to obtain an interleaved vector; and utilize rate matching with the interleaved vector to construct the frozen decode matrix.
6, 13, 20, obtain the final matrix based on the inverse matrix and the first matrix.
1, 8, 15. obtaining, by the device and based on the inverse matrix and the frozen decode matrix, a final matrix;
7, 14. performing additional testing on at least one of the downlink signal or the base station.
The Claims of US patent fail to recite “additional testing”. However, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to include the required testing in the Claims for the purpose of verifying the operational integrity of the base station.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
GE et al. US 20190268094 para. [0048] FIG. 5. A channel is divided into N sub-channels by a polar code as noted above. An information block and frozen bits are allocated onto the N sub-channels, and the resultant N-sized vector is multiplied with an N-by-N Kronecker matrix by the polar encoder 400 to generate a codeword that includes N coded bits.
CHEN et al. US 20190081735 para. [0049] In the embodiments of the present application, the generator matrix is searched for the column with a column weight being 1 and the row in which 1 is located, some or all frozen bits and the puncturing position are determined based on the reliability sequence, and polar encoding and rate matching are performed on the to-be-encoded bit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: February 23, 2026
Non-Final Rejection 20260218
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV