Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed November 26, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 14, 19, 20
b. Pending: 1-20
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
Regarding para. [0007] of the Summary section, on p.2, lines 12-14, add “circuit”, “source”, or another appropriate term after “outside”, for example:
“a power management circuit configured to receive a driving reference voltage from an outside circuit, receive operation timing information…”
Regarding para. [00143] on p.30, line 20, and para. [00170] on p.37, line 5, remove the second period after “etc”.
Regarding para. [00143] on p.31, line 1, make the following change:
“related [[with]]to the voltage rising time of the word line WL”
Regarding para. [0072], on p.16, lines 10-11, make the following change:
“a command input from the host device 200 and transferring the command”
Appropriate correction is required.
Claim Objections
Claims 1, 14, 19, and 20 objected to because of the following informalities:
Regarding claims 1, 14, 19, and 20, add “circuit”, “source”, or another appropriate term after “outside”, for example:
“a power management circuit configured to receive a driving reference voltage from an outside circuit,…”
Regarding claim 19, make the following change to the first and second limitation:
“operation reference voltage that
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 12 on p.3, lines 16-19, is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no mention of “a single port that is included in each of the at least one memory” in the Specification. Para. [00130] describes an “N number of output terminals”, but per Fig. 4, those appear to be located within the switching unit 133.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The last limitation of claim 1, lines 9-12 on p.1, is written in such a way that two interpretations of the following phrase are possible: “output, to the at least one memory, a first operation correction voltage of a first range or a second operation correction voltage of a second range that is adjusted from the driving reference voltage on the basis of the operation timing information.” Specifically, interpretation (1), which the Examiner has used below, is that both the first operation correction voltage and the second operation correction voltage are output on the basis of the operation timing information. Interpretation (2) is that only the second operation correction voltage is output on the basis of the operation timing information. Independent claim 1 and dependent claims 2-13, which depend on independent claim 1, are thus rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Brandt (US Pub. 20250190045 A1).
Regarding independent claim 1, Brandt discloses a storage device (Fig. 2: memory system 210; [0035]) comprising:
at least one memory (memory devices 230; [0035]);
a controller (memory controller 215; [0035]) configured to control an operation of the at least one memory ([0019]: the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices 130; [0035]: For example, the system 200 may include a host system 205, a memory system 210, a memory controller 215…as described with reference to FIG. 1); and
a power management circuit (power management component 220; [0047]) configured to receive a driving reference voltage from an outside ([0047]: The power management component 220 may be coupled with the host system 205 and may be an example of a power management integrated circuit (PMIC) that includes multiple voltage regulators and control circuits to support functions such as battery management, voltage regulation, and charging for the memory system 210), receive operation timing information according to a command transmitted from the controller to the at least one memory, and ([0041]: For example, with the PPM feature turned on, the memory system 210 may update timing parameters corresponding to memory operations to avoid performing the memory operations at multiple memory devices 230 in parallel or during a same or overlapping time periods) output, to the at least one memory, a first operation correction voltage of a first range or a second operation correction voltage of a second range ([0067]: the power management component 345 may be configured as or otherwise support a means for determining, based at least in part on monitoring the one or more power characteristics, that a power state of the memory system is above a second threshold, the one or more power characteristics further including the power state, where determining the load metric is above the first threshold is based at least in part on the power state being above the second threshold) that is adjusted from the driving reference voltage ([0034]: While operating according to the first policy, the memory system 110 may monitor one or more power characteristics of the memory system 110. The one or more power characteristics may include a power state configured for the memory system 110; [0047]) on the basis of the operation timing information ([0041]).
Independent claim 20 is substantially the same in claimed subject matter as
claim 1 and is rejected for the same reasons as independent claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1) as applied to claim 1 above, and further in view of Kim (US Pub. 20180246662 A1).
Regarding claim 2, Brandt discloses the limitations of claim 1. Brandt does not
disclose:
wherein the power management circuit receives, from the controller, operation status information obtained in the at least one memory, and on the basis of the operation status information, adjusts a first operation reference voltage different from the driving reference voltage to the first operation correction voltage or adjusts a second operation reference voltage corresponding to the driving reference voltage to the second operation correction voltage.
However, Kim teaches:
wherein the power management circuit receives, from the controller, operation status information obtained in the at least one memory ([0025]: The power controller 120 may change the levels of power supply voltages to be supplied to the memory device 110 or selectively supply power supply voltages to the memory device 110, based on operation state information of the memory device 110. The operation state information of the memory device 110 may include operation information and temperature information of the memory device 110. The operation information of the memory device 110 may include information on the operation mode of the memory device 110 and a specific operation performed during the operation mode), and on the basis of the operation status information, adjusts a first operation reference voltage different from the driving reference voltage to the first operation correction voltage or adjusts a second operation reference voltage corresponding to the driving reference voltage ([0027]: the power controller 120 may provide the first and second power supply voltages VPP and VDD received from the power source 103 as they are, as the first and second memory power supply voltages MVPP and MVDD. In the first standby operation of the memory device 110, the power controller 120 may supply the first memory power supply voltage MVPP having substantially the same level as the first power supply voltage VPP and may supply the second memory power supply voltage MVDD having a lower level than the second power supply voltage VDD. Alternatively, in the first standby operation, the power controller 120 may supply the second memory power supply voltage MVDD having substantially the same level as the second power supply voltage VDD) to the second operation correction voltage ([0058]: supply the first power supply voltage VPP as the first memory power supply voltage MVPP based on the voltage flag VPPFLAG. Therefore, because the level of the first memory power supply voltage MVPP may be stabilized before the command signal CMD associated with the refresh operation is transmitted, it is possible to prevent time from being lost within the refresh cycle and secure a sufficient refresh operation time).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to Brandt wherein the power management circuit receives, from the controller, operation status information obtained in the at least one memory, and on the basis of the operation status information, adjusts a first operation reference voltage different from the driving reference voltage to the first operation correction voltage or adjusts a second operation reference voltage corresponding to the driving reference voltage to the second operation correction voltage in order to reduce power consumption by providing different power supply voltages to different circuits based on operation state (Kim, [0020], [0042], [0055]).
Regarding claim 5, Brandt and Kim together disclose the limitations of claim 2, and further through Brandt:
wherein at least one of a time point or a cycle at or with which the power management circuit receives the operation status information is different from at least one of a time point or a cycle at or with which the power management circuit receives the operation timing information ([0042]: the memory system 210 may load a first set of trim parameters and upon turning on the PPM feature, the memory system 210 may load a second set of trim parameters that include different operational parameters than the first set of trim parameters).
Regarding claim 6, Brandt and Kim together disclose the limitations of claim 2, and further through Brandt:
wherein the first range is a range that is set on the basis of the first operation reference voltage, and the second range is a range that is set on the basis of the second operation reference voltage ([0042]: Trim parameters may be examples of operational parameters (e.g., voltage parameters) that the memory system 210 may abide by while performing memory operations. Initially (e.g., at power up), the memory system 210 may load a first set of trim parameters and upon turning on the PPM feature, the memory system 210 may load a second set of trim parameters that include different operational parameters than the first set of trim parameters).
Regarding claim 7, Brandt discloses the limitations of claim 1. Brandt does not disclose:
wherein the driving reference voltage is included in the second range.
However, Kim teaches:
wherein the driving reference voltage is included in the second range ([0027]).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to modified Brandt wherein the driving reference voltage is included in the second range in order to reduce power consumption by providing different power supply voltages to different circuits based on operation state (Kim, [0020], [0042], [0055]).
Regarding claim 8, Brandt discloses the limitations of claim 1. Brandt does not disclose:
wherein the first range does not overlap the second range.
However, Kim teaches:
wherein the first range does not overlap the second range ([0027]).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to modified Brandt wherein the first range does not overlap the second range in order to reduce power consumption by providing different power supply voltages to different circuits based on operation state (Kim, [0020], [0042], [0055]).
Regarding claim 9, Brandt discloses the limitations of claim 1. Brandt does not explicitly disclose:
wherein the first operation correction voltage or the second operation correction voltage is applied to at least one word line included in the at least one memory.
However, Kim teaches:
wherein the first operation correction voltage or the second operation correction voltage is applied to at least one word line included in the at least one memory ([0046]: The power controller 220 may provide, to the memory device 210, the first and second memory power supply voltages MVPP and MVDD having optimum levels in consideration of both the various operations and the temperature of the memory device 210; [0024]: The first power supply voltage VPP may be a high voltage or a pumping voltage, and may be a voltage to be supplied to an internal circuit operating with a relatively high voltage level among the internal circuits of the memory device 110. For example, the first power supply voltage VPP may be used in a circuit such as a word line driver. Examiner asserts that these paragraphs show that adjusted power supply voltages are applied to the memory, and more specifically, to word lines. Also, Examiner asserts that it is known in the art that to read or write data, the memory controller, using a word line driver circuit, applies power to a specific word line).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to modified Brandt wherein the first operation correction voltage or the second operation correction voltage is applied to at least one word line included in the at least one memory in order to reduce power consumption by providing different power supply voltages to different circuits based on operation state (Kim, [0020], [0042], [0055]).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1) and Kim (US Pub. 20180246662 A1) as applied to claim 2 above, and further in view of Ogasawara (JP 2004096971 A).
Regarding claim 3, Brandt and Kim together disclose the limitations of claim 2, and further through Kim:
wherein an amplitude of each of the first operation reference voltage and the second operation reference voltage is different from the amplitude of each of the first operation correction voltage and the second operation correction voltage ([0025]: The power controller 120 may change the levels of power supply voltages to be supplied to the memory device 110 or selectively supply power supply voltages to the memory device 110, based on operation state information of the memory device 110), and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to modified Brandt wherein an amplitude of each of the first operation reference voltage and the second operation reference voltage is different from the amplitude of each of the first operation correction voltage and the second operation correction voltage in order to reduce power consumption by providing different power supply voltages to different circuits based on operation state (Kim, [0020], [0042], [0055]).
Neither Brandt nor Kim discloses:
a pulse width of each of the first operation reference voltage and the second operation reference voltage is the same as the pulse width of each of the first operation correction voltage and the second operation correction voltage.
However, Ogasawara teaches:
a pulse width of each of the first operation reference voltage and the second operation reference voltage is the same as the pulse width of each of the first operation correction voltage and the second operation correction voltage ([0035]: The pulse voltage generation means 140 connects and disconnects the first DC voltage generation means 130 and the second DC voltage generation means 150 in accordance with the input pulse signal, thereby generating a pulse voltage having the same pulse width as the pulse signal and the same voltage value as the first DC voltage, and outputs the generated pulse voltage to the second DC voltage generation means 150).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ogasawara to modified Brandt wherein a pulse width of each of the first operation reference voltage and the second operation reference voltage is the same as the pulse width of each of the first operation correction voltage and the second operation correction voltage in order to provide a switching power supply that can change the frequency modulation period of the pulse signal (Ogasawara, [0009]).
Regarding claim 4, Brandt, Kim, and Ogasawara together disclose the limitations of claim 3, and further through Ogasawara:
wherein a number of pulses per unit time of each of the first operation reference voltage and the second operation reference voltage is the same as a number of pulses per unit time of each of the first operation correction voltage and the second operation correction voltage ([0010]: a pulse signal generation means for generating a pulse signal with the same frequency as the oscillation signal).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ogasawara to modified Brandt wherein a number of pulses per unit time of each of the first operation reference voltage and the second operation reference voltage is the same as a number of pulses per unit time of each of the first operation correction voltage and the second operation correction voltage in order to provide a switching power supply that can change the frequency modulation period of the pulse signal (Ogasawara, [0009]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1) as applied to claim 1 above, and further in view of Mori et al. (US Pub. 20040013023 A1; “Mori”).
Regarding claim 10, Brandt discloses the limitations of claim 1. The first two limitations of claim 10 contain substantially the same subject matter as the last limitation of claim 1. Brandt does not disclose:
a switching unit configured to electrically connect the first output and the second output with the at least one memory.
However, Mori teaches:
a switching unit (Fig. 2: switching transistors pMOS 18 and nMOS 20; [0055]) configured to electrically connect the first output (internal power supply line VIIZ; [0064]) and the second output (internal power supply line VSSZ; [0064]) with the at least one memory (memory cell array MA; [0064]-[0065]: the pMOS 18 and the nMOS 20 shown in FIG. 2 are simultaneously turned on…Next, the block selecting signal BLKX is activated in response to the address signal ADD (row address signal) from the exterior, and the word line WL corresponding to the row address signal is activated).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Mori to modified Brandt wherein the power management circuit comprises a switching unit configured to electrically connect the first output and the second output with the at least one memory in order to implement a device decreases current consumption during a standby state without lowering operation speed (Mori, [0010]).
Regarding claim 11, Brandt and Mori together disclose the limitations of claim 10, and further through Mori:
wherein the switching unit (Fig. 2: 18 and 20) electrically connects at least one first memory (MA), which performs a read operation among the at least one memory, and the first output, and electrically connects at least one second memory, which performs a write operation among the at least one memory, and the second output ([0088] FIG. 7 illustrates the MWCL generating circuit 34 and the MRCL generating circuit 36, which are arranged in the circuit block 30. The MWCL generating circuit 34 operates during the write operation of the SDRAM, and serves as a column control circuit for outputting the main write column line signal MWCL and as a read control circuit. The MRCL generating circuit 36 operates during the read operation of the SDRAM, and serves as a column control circuit for outputting the main read column line signal MRCL and as a write control circuit. Examiner notes that circuit block 30 in Fig. 6 is connected to memory cell arrays MA).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Mori to modified Brandt wherein the switching unit electrically connects at least one first memory, which performs a read operation among the at least one memory, and the first output, and electrically connects at least one second memory, which performs a write operation among the at least one memory, and the second output in order to implement a device decreases current consumption during a standby state without lowering operation speed (Mori, [0010]).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1) and Mori (US Pub. 20040013023 A1) as applied to claim 10 above, and further in view of Kato et al. (US Pub. 20200319814 A1; “Kato”).
Regarding claim 12, Brandt and Mori together disclose the limitations of claim 10. Neither Brandt nor Mori discloses:
wherein the switching unit is electrically connected to each of the at least one memory through a single port that is included in each of the at least one memory.
However, Kato teaches:
wherein the switching unit (Fig. 11: switch circuit SW; [0146]) is electrically connected to each of the at least one memory (first memory 32; [0146]; [0156]-[0157]: In the first memory 32 shown in FIG. 14, switch circuits SWs (SW1, SW2) are provided for each memory core MCORE, and in response to receiving different switch control signals from the instruction decoder 33, the respective switch circuits SWs operate…The switch control signal includes logic of an address that selects the memory core MCORE. This allows the first memory 32 to operate as two independent memories) through a single port ([0146]: data I/O DIO of a single port type) that is included in each of the at least one memory (Examiner asserts that the port is contained within the first memory 32).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kato to modified Brandt wherein the switching unit is electrically connected to each of the at least one memory through a single port that is included in each of the at least one memory in order to provide a device that efficiently utilizes memory resources such as arithmetic circuits (Kato, [0005]).
Regarding claim 13, Brandt and Mori together disclose the limitations of claim 10. Neither Brandt nor Mori discloses:
wherein the switching unit operates according to the operation timing information or a control signal based on the operation timing information.
However, Kato teaches:
wherein the switching unit (Fig. 11: SW) operates according to the operation timing information or a control signal ([0150]: the switch circuit SW receives a switch control signal…The switch control signal is generated by the instruction decoder 33 shown in FIG. 1) based on the operation timing information ([0044]: Note that instructions supplied to the instruction decoder 33 may be an instruction for executing one operation, a SIMD instruction for executing a plurality of operations or an instruction for executing an operation at a specified number of times. Examiner concludes that the instruction decoder 33, which generates the switch control signal, responds to instructions about operation timing and order).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kato to modified Brandt wherein the switching unit operates according to the operation timing information or a control signal based on the operation timing information in order to provide a device that efficiently utilizes memory resources such as arithmetic circuits (Kato, [0005]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1) in view of Kim (US Pub. 20180246662 A1), Kato (US Pub. 20200319814 A1), and Kim et al. (KR 20170063319 A; “Kim-KR”).
Regarding independent claim 14, Brandt discloses a power management circuit (Fig. 2: 220) comprising:
a voltage output configured to receive a driving reference voltage from an outside ([0047]),
Brandt does not disclose:
and output at least one operation correction voltage that is obtained as the driving reference voltage adjusted according to the voltage adjustment control signal.
a voltage adjuster configured to output a voltage adjustment control signal based on at least one of operation timing information or operation status information received from a controller; and
However, Kim teaches:
and output at least one operation correction voltage that is obtained as the driving reference voltage ([0027])
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Kim to modified Brandt wherein a voltage output outputs at least one operation correction voltage that is obtained as the driving reference voltage in order to reduce power consumption by providing different power supply voltages to different circuits based on operation state (Kim, [0020], [0042], [0055]).
Also, Kato teaches:
adjusted according to the voltage adjustment control signal ([0150])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kato to modified Brandt wherein an operation correction voltage is adjusted according to the voltage adjustment control signal in order to provide a device that efficiently utilizes memory resources such as arithmetic circuits (Kato, [0005]).
Also, Kim-KR teaches:
a voltage adjuster (Fig. 1: operating environment information storage circuit 150; [0023]) configured to output a voltage adjustment control signal (adjustment control signal; [0028]) based on at least one of operation timing information or operation status information received from a controller ([0028]: The operating environment information storage circuit (150) can generate an updated operating parameter based on the operating environment information when the received operating parameter deviates by more than the difference value set from the reference parameter. A control signal for changing the current operating parameter to an updated operating parameter can be applied to the internal circuit (170) through line (L10)); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim-KR to modified Brandt wherein a power management circuit comprises a voltage adjuster configured to output a voltage adjustment control signal based on at least one of operation timing information or operation status information received from a controller in order to provide a device that can store operating environment information when the device is powered on (Kim-KR, [0008]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1), Kim (US Pub. 20180246662 A1), Kato (US Pub. 20200319814 A1), and Kim-KR (KR 20170063319 A) as applied to claim 14 above, and further in view of Mori (US Pub. 20040013023 A1).
Regarding claim 15, Brandt, Kim, Kato, and Kim-KR together disclose the limitations of claim 14. Kim teaches adjusting a voltage “from a first operation reference voltage different from the driving reference voltage” in claim 2, and Brandt teaches a “voltage output outputs a first operation correction voltage” in claims 1 and 10. Neither Brandt, Kim, Kato, nor Kim-KR discloses:
a first operation correction voltage is adjusted at read operation timing
However, Mori teaches:
a first operation correction voltage ([0093]: main read column line signal MRCL) is adjusted at read operation timing ([0093]: During the read operation, the MRCL generating circuit 36 operates in response to the activation of the bank selecting signal BKZ, the sense amplifier activating signal LEX and the read control signal RDX, and the main read column line signal MRCL is activated)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Mori to modified Brandt wherein a first operation correction voltage is adjusted at read operation timing in order to implement a device decreases current consumption during a standby state without lowering operation speed (Mori, [0010]).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1), Kim (US Pub. 20180246662 A1), Kato (US Pub. 20200319814 A1), Kim-KR (KR 20170063319 A), and Mori (US Pub. 20040013023 A1) as applied to claim 15 above, and further in view of Pan et al. (WO 2022236467 A1; “Pan”).
Regarding claim 16, Brandt, Kim, Kato, Kim-KR, and Mori together disclose the limitations of claim 15. Neither Brandt, Kim, Kato, Kim-KR, nor Mori discloses:
wherein the voltage output outputs a second operation correction voltage that is adjusted from a second operation reference voltage corresponding to the driving reference voltage at write operation timing according to the operation timing information.
However, Pan teaches:
wherein the voltage output outputs a second operation correction voltage that is adjusted from a second operation reference voltage corresponding to the driving reference voltage at write operation timing according to the operation timing information ([0024]: By adopting the above scheme, the stable voltage value of the drive signal when the drive circuit 601 writes data can be obtained by simulating the process of the drive circuit driving the memory array to write data. After reaching the stable value, the effective writing time begins, and the stable value is used as the reference voltage to be output to the control circuit. The control module circuit can control the write auxiliary current generation circuit to output the write auxiliary current when the voltage value of the drive signal has not reached the reference voltage, and control the write auxiliary current generation circuit to stop outputting the write auxiliary current when the voltage value of the drive signal reaches the reference voltage).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Pan to modified Brandt wherein the voltage output outputs a second operation correction voltage that is adjusted from a second operation reference voltage corresponding to the driving reference voltage at write operation timing according to the operation timing information in order to provide a memory and an I/O that reduces data write time (Pan, [0010]).
Regarding claim 17, Brandt, Kim, Kato, Kim-KR, Mori, and Pan together disclose the limitations of claim 16. Claim 17 recites substantially the same limitations as claim 10, and henceforth is rejected for the same reasons.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1), Kim (US Pub. 20180246662 A1), Kato (US Pub. 20200319814 A1), Kim-KR (KR 20170063319 A), Mori (US Pub. 20040013023 A1), and Pan (WO 2022236467 A1) as applied to claim 17 above, and further in view of Do et al. (US Pub. 20220383932 A1; “Do”).
Regarding claim 18, Brandt, Kim, Kato, Kim-KR, Mori, and Pan together disclose the limitations of claim 17. Neither Brandt, Kim, Kato, Kim-KR, Mori, nor Pan discloses:
wherein each of the plurality of output terminals is electrically connected in correspondence to each of a plurality of memories.
However, Do teaches:
wherein each of the plurality of output terminals (Fig. 7: plurality of switch circuits 7301 through 730i; [0060]) is electrically connected in correspondence to each of a plurality of memories (memory cell arrays 2080; [0098]: In the switch circuit 730, which is connected to non-selected memory blocks, e.g., the second through i-th memory blocks BLK2 through BLKi in FIG. 7).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Do to modified Brandt wherein each of the plurality of output terminals is electrically connected in correspondence to each of a plurality of memories in order to provide a word line driver that reduces gate stress on word line driver transistors (Do, [0002]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Brandt (US Pub. 20250190045 A1) in view of Kim (US Pub. 20180246662 A1), Mori (US Pub. 20040013023 A1), Do (US Pub. 20220383932 A1), and Tassan Caser et al. (US Pub. 5822247 A; “TC”).
Independent claim 19 contains a first and second limitation that are substantially the same in claimed subject matter as claims 2 and 10, and those limitations are thus rejected for the same reasons using Brandt, Kim, and Mori. Mori discloses a switching unit that electrically connects outputs, and Do discloses a plurality of output terminals. Neither Brandt, Kim, nor Mori discloses:
a switching unit including a plurality of switches, wherein at least two switches among the plurality of switches are electrically connected simultaneously to the first output or the second output.
However, TC teaches:
a switching unit (Fig. 3: device 14; col. 4, lines 53-59) including a plurality of switches (upper regulator block 23 is one switching unit because per Fig. 4 and col. 5, lines 34-38, it is controlled by a switch, and the combination of the programming switching block 68 and the lower regulator block 27 is another switching unit because per Fig. 5 and col. 6, lines 64-67, switching block 68 contains a high voltage switch. 68 and 27 are connected, so Examiner asserts they can function as a single component), wherein at least two switches among the plurality of switches are electrically connected simultaneously (col. 5, lines 31-37: FIG. 4 shows the upper regulator block 23 which is activated by the enable signal pump_on each time the charge pump of the generator block 15 is operating. Examiner concludes that upper regulator block 23 is usually “on” and therefore electrically connected. Examiner asserts that Fig. 6 shows the on state for the programming switching block 68, and asserts both switches may be on simultaneously since 23 is usually turned on. Further, per the abstract, the switching blocks of Fig. 3 are arranged in parallel, and thus they may operate in parallel) to the first output (output terminal 22; col. 6, lines 16-17) or the second output (col. 4, lines 65-67: The regulator block 27 also contains an output terminal 36 connected to an output terminal 67 of a programming switching block 68).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of TC to modified Brandt wherein there is a switching unit including a plurality of switches, wherein at least two switches among the plurality of switches are electrically connected simultaneously to the first output or the second output in order to provide a gate voltage generating and regulating device that selects the correct gate voltage for optimizing data change in a cell (TC, col. 3, lines 19-24).
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Lee (US Pub. 20230162779 A1): paras. [0028], [0045], and [0084], and Figs. 1-3, 7, and 9-11 are relevant to claims 1, 14, 19, and 20.
Li et al. (US Pub. 20220383929 A1; “Li”): paras. [0043] and [0159]-[0160], and Fig. 8 are relevant to claims 1, 14, 19, and 20.
Palmer (US Pub. 20210286532 A1): paras. [0034] and [0043]-[0044], and Fig. 2 are relevant to claims 1, 14, 19, and 20.
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/E.R.A./ Examiner, Art Unit 2824
/SULTANA BEGUM/ Primary Examiner, Art Unit 2824
7/10/2026
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