Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 11
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in India on September 3, 2024. It is noted, however, that applicant has not filed a certified copy of the Indian application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) are submitted on 11/26/2024 and 10/16/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
Independent claim 1 recites PMOS driver, NMOS driver, variable gate voltage generation circuit, pull-up stop signal generation circuit and pull-down stop signal generation circuit without any details of how they are connected to each other. Figs. 4, 7 and corresponding sections of the Specification describe the exact way these elements are connected.
Independent claim 1 further recites “wherein a second driver output from the NMOS driver is provided after the pull-up calibration stop signal is generated”; it is unclear where the output from NMOS driver is provided to.
All the dependent claims 2-10 carry the same deficit and henceforth are rejected.
Claim 4 recites additional circuit components without clarifying connectivity.
Independent claim 11 recites the same elements and lacks necessary structural connections.
Claim 15 recites additional circuit components without clarifying connectivity.
All the dependent claims 12-20 carry the same deficit and henceforth are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sreeramaneni et al. (US 20100182014).
Regarding independent claim 1, Sreeramaneni discloses a circuit (30; Fig. 2) for calibrating analog signals on a scalable memory interface driver (Figs. 2-4), the circuit comprising:
a p-channel metal-oxide semiconductor (PMOS) driver (202; Fig. 2);
an n-channel metal-oxide semiconductor (NMOS) driver (204; Fig. 2);
a variable gate voltage generation circuit (54, 88; Fig. 2);
a pull-up stop signal generation circuit (Fig. 2 shows circuit 54 generates output signal); and
a pull-down stop signal generation circuit (Fig. 2 shows circuit 88 generates output signal);
wherein the circuit is configured to:
provide a first variable voltage to the PMOS driver from the variable gate voltage generation circuit (Fig. 2 shows circuit 54 provides signal to pmos driver 202), wherein a transistor of the PMOS driver is configured to receive a power supply voltage (Fig. 2 and [0007] describes supply voltage 206 connected to transistor 62), and a first driver output of the PMOS driver is connected to an external resistor (34; Fig. 2);
stop the first variable voltage from changing by disconnecting a first current source according to a pull-up calibration stop signal, based on identifying that the first driver output is greater than a reference value (Fig. 2 and [0007] describes that voltage at the calibration terminal is coupled to pull-up calibration logic 54. Responsive to a calibration command, the pull-up driver 202 is turned on, and the pull-up calibration logic may compare the voltage at the calibration terminal 32 with a reference voltage, V.sub.ref, and adjust the p-channel variable impedance circuit 62 to achieve a desired voltage at the calibration terminal 32);
provide a second variable voltage to the NMOS driver from the variable gate voltage generation circuit, wherein a second driver output from the NMOS driver is provided after the pull-up calibration stop signal is generated (Figs. 2-4 and [0019] describes that calibration circuit 30 performs a calibration routine between time 415 and time 460 while the comparator 320 determines a state of the calibration pad 32 between the time 415 and 420. The calibration time between times 415 and 460 includes a first time for calibrating using the pull-up driver followed by a second time for calibration using the pull-down driver, as generally described above with reference to FIG. 2. The pull-up driver calibration time is between the time 415 and the time 430, and the pull-down calibration time between time 430 and time 460); and
stop the second variable voltage from changing by disconnecting a second current source according to using a pull-down calibration stop signal, based on the second driver output from the NMOS driver being less than the reference value (Fig. 2 and [0007] describes that pull-down calibration logic 88 compares a voltage at a node 64 to the reference voltage V.sub.ref and adjusts an impedance of an n-channel variable impedance circuit 84. In this manner, the voltage at the node 64 may also be adjusted).
Regarding claim 2, Sreeramaneni discloses all the elements of claim 1 as above and further comprising a comparator (320; Fig. 3), wherein the circuit is further configured to: switch an output of the comparator from one to zero, based on the first driver output being greater than the reference value, wherein the reference value is a reference voltage provided to the comparator; and lock a pull-up generation signal in a pull-up voltage generation circuit, based on the pull-up calibration stop signal switching from one to zero (Fig. 3 and [0019]-[0022] describes operation of comparator).
Regarding claim 3, Sreeramaneni discloses all the elements of claim 1 as above and further comprising a comparator (320; Fig. 3) and a pull-down signal generation circuit (Fig. 2), wherein the circuit is further configured to, based on a driver output being less than the reference value, switch an output of the comparator from zero to one, and based on the pull-down calibration stop signal switching from zero to one, lock a pull-down generation signal in the pull-down stop signal generation circuit (Fig. 3 and [0019]-[0022] describes operation of comparator).
Regarding claim 6, Sreeramaneni discloses all the elements of claim 1 as above and further a comparator (320; Fig. 3); and a calibration stop signal generation circuit configured to use the external resistor (34; Fig. 2) and the comparator to generate the pull-up calibration stop signal and the pull-down calibration stop signal based on a comparison of a driver output voltage and a reference voltage (Fig. 3 shows that VREF and output from block 32 being compared and output is being generated. Fig. 3 shows that VREF and pull-down signal 64 being compared and output is being generated), wherein the reference voltage is an input voltage to the comparator (320; Fig. 3).
Regarding claim 7, Sreeramaneni discloses all the elements of claim 1 as above and further the circuit is further configured to set a driver impedance by varying the first variable voltage and the second variable voltage (Fig. 2 and [0007]-[0009] describes that based on the adjustments necessary to the p-channel variable impedance circuit 62 and the n-channel variable impedance circuit 84, the pull-up and pull-down calibration logic couple respective control signals 106 and 108 to the output circuit for use in configuring the output impedance of the output buffers).
Regarding claim 8, Sreeramaneni discloses all the elements of claim 1 as above and further the circuit is further configured to set a pull-up driver impedance, and a pull-down driver impedance by varying the first variable voltage and the second variable voltage, respectively (Fig. 2 and [0007]-[0009]).
Regarding claim 10, Sreeramaneni discloses all the elements of claim 1 as above and further the circuit is further configured to limit a gate-to-source voltage of the PMOS driver and the NMOS driver (Fig. 2).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Sreeramaneni et al. (US 20100182014) in view of DEKA ANUPJYOTI ET AL: "A Jitter Cancellation Circuit for High Speed I/O Interfaces",
2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE
(SOCC), IEEE, 6 September 2016 (2016-09-06), pages 157-162, XP033086783, herein referred as Deka.
Regarding claim 4, Sreeramaneni discloses all the elements of claim 1 as above and through Deka further the variable gate voltage generation circuit comprises a current source, a current mirror, at least one metal-oxide semiconductor (MOS) device, and at least one capacitor to generate the first variable voltage, and wherein the first variable voltage is variable set based on a supply voltage (Fig. 4 shows all the recited components).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Deka to modified Sreeramaneni in order to provide with improved jitter cancellation circuit as taught by Deka ([Abstract).
Regarding claim 5, Sreeramaneni and deka together disclose all the elements of claim 4 as above and through Deka further a lower supply voltage generation path and a higher ground voltage generation path are formed along the current source, a bias generation circuit, the current mirror, the at least one MOS device and the at least one capacitor (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Deka to modified Sreeramaneni in order to provide with improved jitter cancellation circuit as taught by Deka ([Abstract).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sreeramaneni et al. (US 20100182014) in view of Huang et al. (US 20210242659).
Regarding claim 9, Sreeramaneni and deka together disclose all the elements of claim 1 as above and through Huang further the circuit is further configured to: use the first variable voltage as an elevated ground voltage; and use the second variable voltage as a reduced supply voltage (Fig. 8 and [0038]-[0040] and [0044]).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Huang to modified Sreeramaneni in order to provide with a resonant circuit coupled to a driver circuit as taught by Huang ([0003]).
Claims 11-20 recites same limitations of device claims 1-10 but drafted in method format and henceforth rejected the same way as above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Choi (US 10748585)
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 8/3/2026
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