DETAILED ACTION
This non-final action is responsive to communications: application filed on 11/27/2024.
Claims 1-11 are pending. Claims 1 and 8 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
No Information Disclosure Statement
5. No IDS is in the record.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claims 1, 3-4, and 8 is/are rejected under 35 U.S.C. 103 as being obvious over Lee et al. (US 2023/0370082 A1), in view of Thibadeau et al. (US 2009/0024816 A1).
Regarding independent claim 1, Lee teaches a processing-in-memory device based on a resistive memory (Fig. 2: 200 “in-memory computing Macro” for performing “Charge-domain in-memory computing”, see e.g., para [0040], para [0004], para [0048]),
the processing-in-memory device comprising:
at least one local array (“IMC Column”, see Fig. 2, Fig. 5); and
an input operation unit (para [0040]: combined “periphery for providing…input-vector elements” and “column reset mechanisms”) configured to re-set an input value based on (para [0041]: “…MVM operations are typically performed by applying input-vector element corresponding to neural-network input activations…”. Thus digital 5-bit inputs are restarted corresponding to operation requirements. Additionally, see column reset) with respect to an operation of the local array (para [0041]) and to apply the re-set input value to the local array (para [0041]: restarted 5-bit inputs corresponding to operation requirements is used), and
wherein the local array (“IMC Column”, see Fig. 2, Fig. 5) includes:
at least one weight cell (Fig. 3: SRAM latch portion of 10T cell) configured to store a plurality of weights (par [0046], para [0007]); and
a charge domain cell (Fig. 3: C, SW1, SW2 circuitry portion of 10T cell; see para [0041], para [0045]) configured to convert the stored weights into voltage values based on the re-set input value (para [0041]: “…DRD-DAC 2201, in response to a respective 5-bit input vector element X…generates …output signal (IA/ IAb) which is subjected to a 1-bit multiplication with the stored weights (W, /Wb,) … and accumulation through charge-redistribution across M-BC capacitors on the compute line…”. See also para [0047]).
Lee is silent with respect to an input operation unit configured to re-set an input value based on a predicted value and to apply the re-set input value to the local array.
Thibadeau teaches an input operation unit (input data employing “NSLP system” and “NSLP function”, see para [0022], para [0027]) configured to re-set an input value based on a predicted value and to apply the re-set input value to the local array (“…The input field may also contain past input state data or predicted input state data …past input data may also contain reset data to reset the NLSP system to a prior state”. see e.g., Fig. 1-Fig. 2, para [0027]-para [0028]).
Lee and Thibadeau are in the same field of endeavor of operational method (programming weights and analog compute) of neural network and they are in the analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Thibadeau’s NLSP system and function into the apparatus of Lee such that input operation unit can be employed to re-set an input value based on a predicted value in order to have capability of non-linear processing of large number of combination data units and thus improve system performance (Thibadeau para [0030]).
Regarding claim 3, Lee and Thibadeau teach the processing-in-memory device of claim 1. Lee teaches wherein the local array (“IMC Column”, see Fig. 2, Fig. 5) performs a multiplication-accumulation operation by charge sharing source line (Fig. 2, Fig. 3, Fig. 5: CL) voltage values of the charge domain cell (Fig. 2, Fig. 4B in context of para [0041], para [0058], para [0011]).
Regarding claim 4, Lee and Thibadeau teach the processing-in-memory device of claim 3. Lee teaches further comprising: at least one sample and hold circuit configured to store a result value of the multiplication-accumulation operation (Fig. 2 in context of para [0010], para [0011]: “…sample and hold circuit associated with an input of an analog to digital converter…”); and
an analog-to-digital conversion circuit configured to charge-share the result values stored in the at least one sample and hold circuit and to convert the result values into digital values (Fig. 2 in context of para [0010], para [0011], para [0041]).
Regarding independent claim 8, Lee and Thibadeau teach a method of operating a processing-in-memory device based on a resistive memory, the method comprising: storing a plurality of weights;
re-setting an input value based on a predicted value with respect to an operation of a local array;
applying the re-set input value to the local array;
converting the stored weight into a voltage value based on the re-set input value;
performing a multiplication-accumulation operation by charge sharing the voltage value;
storing a result value of the multiplication-accumulation operation; and charge sharing the stored result values and converting the result values into digital values.
(Method claim 8 limitations are substantially identical to apparatus claim 1 limitations: see claim 1 limitation analysis where Lee teaches a processing-in-memory device based on a resistive memory (Fig. 2: 200 “in-memory computing Macro” for performing “Charge-domain in-memory computing”, see e.g., para [0040], para [0004], para [0048]), the processing-in-memory device comprising: at least one local array (“IMC Column”, see Fig. 2, Fig. 5); and an input operation unit (para [0040]: combined “periphery for providing…input-vector elements” and “column reset mechanisms”) configured to re-set an input value based on a predicted value (para [0041]: “…MVM operations are typically performed by applying input-vector element corresponding to neural-network input activations…”. Thus digital 5-bit inputs are restarted corresponding to operation requirements. Additionally, see column reset) with respect to an operation of the local array (para [0041]) and to apply the re-set input value to the local array (para [0041]: restarted 5-bit inputs corresponding to operation requirements is used), and wherein the local array (“IMC Column”, see Fig. 2, Fig. 5) includes: at least one weight cell (Fig. 3: SRAM latch portion of 10T cell) configured to store a plurality of weights (par [0046], para [0007]); and a charge domain cell (Fig. 3: C, SW1, SW2 circuitry portion of 10T cell; see para [0041], para [0045]) configured to convert the stored weights into voltage values based on the re-set input value (para [0041]: “…DRD-DAC 2201, in response to a respective 5-bit input vector element X…generates …output signal (IA/ IAb) which is subjected to a 1-bit multiplication with the stored weights (W, /Wb,) … and accumulation through charge-redistribution across M-BC capacitors on the compute line…”. See also para [0047]). Thibadeau teaches an input operation unit (input data employing “NSLP system” and “NSLP function”, see para [0022], para [0027]) configured to re-set an input value based on a predicted value and to apply the re-set input value to the local array (“…The input field may also contain past input state data or predicted input state data …past input data may also contain reset data to reset the NLSP system to a prior state”. see e.g., Fig. 1-Fig. 2, para [0027]-para [0028]))
8. Claim 2 is/are rejected under 35 U.S.C. 103 as being obvious over Lee et al. (US 2023/0370082 A1), and Thibadeau et al. (US 2009/0024816 A1), in view of LYU ZHENYU et al. (CN118333119A).
Regarding claim 2, Lee and Thibadeau teach the processing-in-memory device of claim 1.
Lee and Thibadeau are silent with respect to weight cell being resistive memory and charge domain cell being SRAM of a latch structure.
LYU teaches weight cell includes the resistive memory (Fig. 2: 200 in context of pages 9-10: nonvolatile ferroelectric cells), and
charge domain cell includes a static random-access memory (SRAM) of a latch structure (Fig. 2: 102 in context of pages 3, 10, abstract of translation: nonvolatile ferroelectric cells).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the computing unit structure of LYU into the apparatus of Lee and Thibadeau such that claimed limitation can be employed in order to have benefits “…memory computing circuit adopts a nonvolatile memory unit, so that data can be ensured not to be lost when power is off, and the power consumption overhead is greatly reduced…” (LYU: Abstract)
Allowable Subject Matter
Claims 5-7, and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims as described in details in the following:
Claim 5. The processing-in-memory device of claim 3, wherein the predicted value is a result of performing the multiplication-accumulation operation on the weight and the input value, and wherein the input operation unit, when the predicted value is “0”, re-sets the input value to “0”.
Claims 6-7. The processing-in-memory device of claim 2, wherein the at least one weight cell is configured to: store a weight based on a weight pattern of a filter among the plurality of weights, and when the weight pattern is repeated among the plurality of weights, remove the weight.
Claim 9. The method of claim 8, wherein the predicted value is a result of performing the multiplication-accumulation operation on the weight and the input value, and wherein the re-setting of the input value includes, when the predicted value is “0”, re-setting the input value to “0”.
Claims 10-11. The method of claim 8, wherein the storing of the plurality of weights includes storing a weight based on a weight pattern of a filter among the plurality of weights; and removing the weight when the weight pattern is repeated among the plurality of weights.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Yuh (US 20240296887 A1): Fig. 1-Fig. 10 disclosure applicable for all claims.
Ma (US 9,349,440 B1) is applicable for all claims. Ma teaches an integrated circuit (Fig. 1: 100 “nvSRAM device”. See also Fig. 2 and Fig. 3 configuration applicable for the rejection)
KWON (US 2024/0061649 A1): Fig. 1-Fig. 9 disclosure applicable for all claims.
Yang (US 2025/0156149 A1): Fig. 1-Fig. 4 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825