DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 28, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuge (U.S. Patent Pub. No. 2013/0335399; already of record) in view of Lee et al (U.S. Patent Pub. No. 2024/0177674; already of record).
Regarding claim 1, Tsuge discloses a pixel (12), (fig. 9, [0081]), comprising:
a first transistor (Q20) including a first electrode connected to a first power line (31), a first gate electrode connected to a first node (Tp1), and a second electrode connected to a second node (Tp2) through capacitor C22, (fig. 9, [0082, 0084 and 0085]);
a second transistor (Q22) connected between a data line (20) and the first node (Tp1), and including a gate electrode connected to a first scan line (22), (fig. 9, [0042 and 0084]);
a light emitting element (D20) including a first electrode (anode) connected to the second electrode of the first transistor (Q20), and a second electrode (cathode) connected to a second power line (32), (fig. 9, [0039, 0081 and 0098]);
a first capacitor (C21) and a second capacitor (C22) connected in series, wherein the first capacitor is connected between the first node (Tp1) and the second node (Tp2) and the second capacitor is connected directly between the second node (Tp2) and the first electrode (anode) of the light emitting element (D20), (fig. 9, [0081]).
However, Tsuge does not mention a first transistor including a second electrode directly connected to a second node.
In a similar field of endeavor, Lee teaches a pixel circuit, (fig. 16, [0130]), comprising:
a first transistor (DT) including a first electrode connected to a first power line (41) through transistor M04, a first gate electrode connected to a first node (n1), and a second electrode directly connected to a second node (n2), (fig. 16, [0132 and 0136]);
a first capacitor (Cst) and a second capacitor (C2) connected in series, wherein the first capacitor (Cst) is connected between the first node (n1) and the second node (n2) and the second capacitor is connected directly to the second node (n2), (fig. 16, [0127 and 0139]); and
a sixth transistor (M05) connected directly between the second node (n2) and the first electrode (n4) of the light emitting element (EL), (fig. 16, [0131 and 0137]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge, by specifically providing the first transistor including the second electrode directly connected to the second node, as taught by Lee, for the purpose of possibly realizing a simple structure, [0015].
Regarding claim 3, Tsuge discloses wherein the pixel further comprising:
a third transistor (Q44) connected between a third power line (33) and the first node (Tp1), and including a gate electrode connected to a second scan line (44), (fig. 9, [0082]); and
a fourth transistor (Q23) connected between the first electrode of the light emitting element (D20) and a fourth power line (34), and including a gate electrode connected to a third scan line (23), (fig. 9, [0084 and 0087]).
Regarding claim 5, Tsuge discloses wherein when the second transistor (Q22) is turned on, the fourth transistor (Q23) is set to a turn-off state (i.e. during period T3, Q22 is on and Q23 is off), (fig. 11, [0107]).
Regarding claim 6, Tsuge discloses wherein
a turn-on period of the third transistor (Q44) and a turn-on period of the fourth transistor (Q23) overlap during some periods (i.e. overlap during period T1), (figs. 9 and 11, [0084]), and
a turn-on period of the second transistor (Q22) and the turn-on period of the third transistor (Q44) do not overlap (i.e. Q22 and Q44 do not overlap during period T3), (figs. 9 and 11, [0089]).
Regarding claim 7, Lee discloses further comprising:
a fifth transistor (M04) connected between the first power line (41) and the first electrode of the first transistor (DT), and including a gate electrode connected to a first emission control line (EM1), (fig. 16, [0136]); and
the sixth transistor (M05) includes a gate electrode connected to a second emission control line (EM2), (fig. 16, [0137]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge, by specifically providing the fifth transistor, as taught by Lee, for the purpose of possibly realizing a simple structure, [0015].
Claim(s) 2, 4, 10-11, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuge in view of Lee and in view of Kim et al (U.S. Patent Pub. No. 2023/0036497; already of record).
Regarding claim 2, Lee discloses wherein:
the first capacitor (Cst) is directly connected between the first node (n1) and the second node (n2), (fig. 16, [0138]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge, by specifically providing the first capacitor directly connected between the first node and the second node, as taught by Lee, for the purpose of possibly realizing a simple structure, [0015].
However, Tsuge in view of Lee does not mention the first transistor further includes a second gate electrode.
In a similar field of endeavor, Kim teaches wherein:
the first capacitor (Cst) is directly connected between the first node (N1) and the second node (N3),
the first transistor (T1) further includes a second gate electrode, and
the second gate electrode is connected to the second node (N3), (fig. 2, [0088 and 0090]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the first transistor having the back gate electrode, as taught by Kim, for the purpose of reducing power consumption, [0197].
Regarding claim 4, Kim discloses wherein when the second transistor (T2) is turned on, the fourth transistor (T4) is set to a turn-on state (i.e. both T2 and T4 are turned on during period P3), (figs. 2 and 4, [0146 and 0148]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the second and fourth transistor are turned on, as taught by Kim, for the purpose of reducing power consumption, [0197].
Regarding claim 10, Tsuge discloses a display device (10), (fig. 1, [0033]), comprising:
a pixel component including pixels (12) connected to scan lines (21-24) and data lines (20), (fig. 1, [0034]);
a scan driver (16) that drives the scan lines (21-24), (fig. 1, [0034]);
a data driver (14) that drives the data lines (20), (fig. 1, [0034]); and
wherein one of the pixels (12) connected to an i-th horizontal line and a j-th data line (where i and j each are a natural number), (fig. 1, [0033]), comprises:
a first transistor (Q20) including a first electrode connected to a first power line (31), a first gate electrode connected to a first node (Tp1), and a second electrode connected to a second node (Tp2) through capacitor C22, (fig. 9, [0082, 0084 and 0085]);
a second transistor (Q22) that is connected between a data line (20) and the first node (Tp1), and turned on when a first enable scan signal (CNT22) is supplied to a first scan line (22) of an i-th scan line, (fig. 9, [0042 and 0084]);
a light emitting element (D20) including a first electrode connected to the second electrode of the first transistor (Q20), and a second electrode connected to a second power line (32), (fig. 9, [0081 and 0098]);
a first capacitor (C21) and a second capacitor (C22) connected in series, wherein the first capacitor (C21) is connected between the first node (Tp1) and the second node (Tp2) and the second capacitor (C22) is connected directly between the second node (Tp2) and the first electrode (anode) of the light emitting element (D20), (fig. 9, [0040 and 0081]).
However, Tsuge does not mention emission control lines.
In a similar field of endeavor, Lee teaches
a pixel component (AA) including pixels connected to scan lines (103), emission control lines (EM), and data lines (102), (fig. 1, [0041, 0060-0061, 0064]);
an emission driver (122) that drives the emission control lines (EM), (fig. 1, [0064]),
a first transistor (DT) including a first electrode connected to a first power line (41) through transistor M04, a first gate electrode connected to a first node (n1), and a second electrode directly connected to a second node (n2), (fig. 16, [0132 and 0136]); and
a sixth transistor (M05) connected directly between the second node (n2) and the first electrode (n4) of the light emitting element (EL), (fig. 16, [0131 and 0137]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge, by specifically providing the first transistor including the second electrode directly connected to the second node, as taught by Lee, for the purpose of possibly realizing a simple structure, [0015].
However, Tsuge in view of Lee does not mention a first transistor including a second gate electrode directly connected to a second node.
In a similar field of endeavor, Kim teaches a first transistor (T1) including a first electrode connected to a first power line (PL1), a first gate electrode connected to a first node (N1), and a second electrode and a second gate electrode (back gate electrode) each directly connected to a second node (N3), (fig. 2, [0088 and 0090]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the first transistor having the back gate electrode, as taught by Kim, for the purpose of reducing power consumption, [0197].
Regarding claim 11, Tsuge discloses wherein the first capacitor (C21) is directly connected between the first node (Tp1) and the second node (Tp2), (fig. 9, [0040]), and the one of the pixels (12) further comprises:
a third transistor (Q44) that is connected between a third power line (33) and the first node (Tp1), and turned on when a second enable scan signal (CNT44) is supplied to a second scan line (44) of the i-th scan line, (fig. 9, [0082]); and
a fourth transistor (Q23) that is connected between the first electrode of the light emitting element (D20) and a fourth power line (34), and turned on when a third enable scan signal (CNT23) is supplied to a third scan line (23) of the i-th scan line, (fig. 9, [0084 and 0087]).
Regarding claim 17, Kim discloses wherein
first driving power (VDD) is supplied to the first power line (PL1), (fig. 2, [0089]),
second driving power (VSS) having a voltage lower than the first driving power (VDD) is supplied to the second power line (PL2), (fig. 2, [0089]),
a voltage of reference power (Vref) is supplied to the third power line (PL3), (fig. 2, [0093]), and
a voltage of initialization power (Vint) is supplied to the fourth power line (PL4), (fig. 2, [0095]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the first through fourth power line, as taught by Kim, for the purpose of reducing power consumption, [0197].
Regarding claim 18, Kim discloses wherein each of the reference power (Vref) and the initialization power (Vint) maintains a constant voltage, (fig. 2, [0093 and 0095]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the reference and initialization power, as taught by Kim, for the purpose of reducing power consumption, [0197].
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuge in view of Lee and in view of Heo et al (U.S. Patent Pub. No. 2024/0257757; already of record).
Regarding claim 8, Lee discloses everything as specified above in claim 7. However, Tsuge in view of Lee does not mention the sixth transistor has a turn-on period overlapping a turn-on period of the third transistor during a first period.
In a similar field of endeavor, Heo teaches wherein
the sixth transistor (M5) has a turn-on period overlapping a turn-on period of the third transistor (M4) during a first period (i.e. during period INI), (figs. 11-12, [0125-0126 and 0128]),
the fifth transistor (M6) has a turn-on period overlapping the turn-on period of the third transistor (M4) during a second period (i.e. during period SEN), (figs. 11-12, [0125, 0127 and 0129]), and
the first period (period INI) and the second period (period SEN) do not overlap, (fig. 12, [0128-0129]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the fifth and sixth transistor, as taught by Heo, for the purpose of preventing data transmission loss, [0007].
Regarding claim 9, Lee discloses wherein the fourth transistor (M02) is set to a turn-on state during the first period (initial period) and the second period (sensing period) during the display mode, (figs. 16-17, [0146]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge, by specifically providing the first transistor including the second electrode directly connected to the second node, as taught by Lee, for the purpose of possibly realizing a simple structure, [0015].
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuge in view of Lee in view of Kim and in view of Heo.
Regarding claim 12, Kim discloses wherein the one of the pixels (13) further comprises:
a fifth transistor (T5) that is connected between the first power line (PL1) and the first electrode of the first transistor (T1), and turned off when a first disable emission control signal (ESi) is supplied to a first emission control line (Ei) of an i-th emission control line; and
a sixth transistor (T8) that is connected between the second node and the first electrode of the light emitting element (LD), and turned off when the first disable emission control signal (ESi) is supplied to the first emission control line (Ei) of the i-th emission control line, (fig. 8, [0097 and 0192]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the fifth and sixth transistor, as taught by Kim, for the purpose of reducing power consumption, [0197].
However, Tsuge in view of Lee and in view of Kim does not mention a second disable emission control signal.
In a similar field of endeavor, Heo teaches
a sixth transistor (M5) that is connected between the second node and the first electrode of the light emitting element (EL), and turned off in case that a second disable emission control signal (EM1) is supplied to a second emission control line (GL5) of the i-th emission control line, (fig. 11, [0085]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee and in view of Kim, by specifically providing the second disable emission control signal, as taught by Heo, for the purpose of preventing data transmission loss, [0007].
Regarding claim 13, Tsuge discloses wherein
the one of the pixels (12) is driven with a first period (T1), a second period (T2), a third period (T3), and a fourth period (T4) divided from each other, and
the scan driver (16) supplies the second enable scan signal (CNT44) and the third enable scan signal (CNT23) during the first period (T1) and the second period (T2), and supplies the first enable scan signal (CNT22) during the third period (T3), (figs. 9 and 11, [0102-0107]).
Regarding claim 14, Kim discloses wherein the scan driver (300) supplies the third enable scan signal (SS2i) during the third period (P3), (figs. 2 and 4, [0146-0147]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee, by specifically providing the third enable scan signal during the third period, as taught by Kim, for the purpose of reducing power consumption, [0197].
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuge in view of Lee in view of Kim in view of Heo and in view of Yang et al (U.S. Patent Pub. No. 2023/0112488; already of record).
Regarding claim 15, Tsuge discloses everything as specified above in claim 13. However, Tsuge in view of Lee in view of Kim and in view of Heo does not mention the first disable emission control signal during the first period and the third period.
In a similar field of endeavor, Yang teaches
wherein the emission driver (300) supplies the first disable emission control signal (E1i) during the first period (P1) and the third period (P3), and supplies the second disable emission control signal (E2i) during the second period (P2) and the third period (P3) (i.e. when emission control signals E1i and E2i are at a high level, it disables the transistors M6 and M7, respectively), (figs. 4-5, [0100-0103]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee in view of Kim and in view of Heo, by specifically providing the first disable emission control signal during the first period and the third period, as taught by Yang, for the purpose of providing a pixel that secures a compensation period, [0006].
Regarding claim 16, Heo discloses wherein
the emission driver (120) supplies a first enable emission control signal (EM2) to the first emission control line (GL6) during the fourth period (EMIS) to turn on the fifth transistor (M6), and
the emission driver (120) supplies a second enable emission control signal (EM1) to the second emission control line (GL5) during the fourth period (EMIS) to turn on the sixth transistor (M5), (figs. 1 and 11-12, [0066 and 0126-0127]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Tsuge in view of Lee and in view of Kim, by specifically providing the enable emission control signals, as taught by Heo, for the purpose of preventing data transmission loss, [0007].
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim and in view of Tsuge.
Regarding claim 19, Lee discloses an electronic device (fig. 1) comprising:
a display module (100) that displays an image, (fig. 1, [0041]);
a sensing module (160) that senses an input (i.e. sense a current flow) corresponding to the image displayed on the display module (100), (fig. 4, [0086-0088]);
a processor (130) and an auxiliary processor (130) that controls the display module (100) and the sensing module (160), (fig. 4, [0055 and 0088]); and
a display panel (100) including the display module (100), and displaying the image, (fig. 1, [0041]),
wherein at least one pixel (101) included in the display panel (100) comprises:
a first transistor (DT) including a first electrode connected to a first power line (41), a first gate electrode connected to a first node (n1), and a second electrode directly connected to a second node (n2), (fig. 16, [0132]);
a second transistor (M01) connected between a data line (40) and the first node (n1), and including a gate electrode connected to a first scan line (SCAN), (fig. 16, [0133]);
a light emitting element (EL) including a first electrode connected to the second electrode of the first transistor (DT) through transistor M05, and a second electrode connected to a second power line (EVSS), (fig. 16, [0131]); and
a first capacitor (Cst) and a second capacitor (C2) connected in series, wherein the first capacitor (Cst) is connected between the first node (n1) and the second node (n2), (fig. 16, [0138-0139]); and
a sixth transistor (M05) connected directly between the second node (n2) and the first electrode (n4) of the light emitting element (EL), (fig. 16, [0131 and 0137]).
However, Lee does not mention a first transistor including a second gate electrode directly connected to a second node.
In a similar field of endeavor, Kim teaches
a first transistor (T1) including a first electrode connected to a first power line (PL1), a first gate electrode connected to a first node (N1), and a second electrode and a second gate electrode (back gate electrode) each directly connected to a second node (N3), (fig. 2, [0088-0090]);
a first capacitor (Cst), wherein the first capacitor is connected between the first node (N1) and the second node (N3), (fig. 2, [0099]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee, by specifically providing the second gate electrode, as taught by Kim, for the purpose of reducing power consumption, [0197].
However, Lee in view of Kim does not mention the second capacitor is directly connected between the second node and the first electrode of the light emitting diode.
In a similar field of endeavor, Tsuge teaches
a first capacitor (C21) and a second capacitor (C22) connected in series, wherein the first capacitor (C21) is connected between the first node (Tp1) and the second node (Tp2) and the second capacitor (C22) is directly connected between the second node (Tp2) and the first electrode (anode) of the light emitting element (D20), (fig. 9, [0040 and 0081]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Kim, by specifically providing the first and second capacitor connected in series, as taught by Tsuge, for the purpose of achieving writing operation at high speed, [0017].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim in view of Tsuge and in view of Heo.
Regarding claim 20, Tsuge discloses wherein the at least one pixel (12) further comprises:
a third transistor (Q44) connected between a third power line (33) and the first node (Tp1), and including a gate electrode connected to a second scan line (44), (fig. 9, [0082]);
a fourth transistor (Q23) connected between the first electrode of the light emitting element (D20) and a fourth power line (34), and including a gate electrode connected to a third scan line (23), (fig. 9, [0084 and 0087]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Kim, by specifically providing the first and second capacitor connected in series, as taught by Tsuge, for the purpose of achieving writing operation at high speed, [0017].
However, Lee in view of Kim and in view of Tsuge does not mention a fifth and sixth transistor.
In a similar field of endeavor, Heo teaches
a fifth transistor (M6) connected between the first power line (EVDD) and the first electrode of the first transistor (DT), and including a gate electrode connected to a first emission control line (EM2); and
a sixth transistor (M5) connected between the second node and the first electrode of the light emitting element (EL), and including a gate electrode connected to a second emission control line (EM1), (fig. 11, [0126-0127]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Lee in view of Kim and in view of Tsuge, by specifically providing the fifth and sixth transistors, as taught by Heo, for the purpose of preventing data transmission loss, [0007].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of amendment, the reference of Lee (fig. 16) has been added for new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Byun et al (U.S. Patent Pub. No. 2024/0135876) discloses a pixel circuit as shown in figure 9.
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/LONG D PHAM/ Primary Examiner, Art Unit 2623
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