DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 11/27/2024. Claims 1-14 are pending in the Application, of which Claims 1 and 7 are independent.
Continuity/ Priority information
The present Application 18961956 filed 11/27/2024 is a Continuation of 18126267, filed 03/24/2023, now U.S. Patent No. 12,183,414, which claims foreign priority to REPUBLIC OF KOREA, Application 10-2022-0129289, filed 10/11/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Toronyi et al. (Pub. No. US20140013070) in view of Takahashi et al. (Pub. No. US 20150037914) Pub. Date: 2015-02-05.
Regarding independent Claims 1 and 7, Toronyi discloses a device and method for dynamic memory performance throttling, comprising:
a memory cell area including a memory cell array; and a peripheral circuit area overlapping with the memory cell area by bonding to the memory cell area,
[0023] FIG. 1 is an illustration of a stacked “overlapping” memory device100 (such as a WideIO memory device) including one more DRAM die layers 120 “a first chip including a memory cell array” that is closely coupled with a logic chip 110 “a second chip overlapping with the first chip”, which may be an SoC or other system element. In some embodiments, the logic chip 110 may include a memory controller. In some embodiments, the memory controller provides for throttling of operation of the memory to address misalignment of signals.
wherein the peripheral circuit area includes: a sub-test pad and an input pad spaced apart from each other; a sub-test circuit connected to the sub-test pad; [0024] FIG. 2 illustrates an embodiment of a 3D stacked memory providing for performance throttling. In this illustration, a 3D stacked memory device 200 includes a logic chip system element 210 “second chip” coupled with one or more DRAM memory die layers 220 “first chip”, also referred to herein as the memory stack, where the memory die layers may include one or more slices or portions, and may include one or more channels. [0026] In this illustration, the DRAM memory die layers include four memory die layers 230, 240, 250, and 260 “first chip”. However, embodiments are not limited to any particular number of memory die layers in the memory stack 220, and may include a greater or smaller number of memory die layers.
a detection circuit configured to output a detection signal according to a signal input from the terminal, wherein the memory cell area includes an upper test pad overlapping with a portion of the peripheral circuit area , wherein the upper test pad is bonded and connected to the input pad,
FIG. 2 illustrates an implementation in which the logic chip 210 is coupled below the memory stack of one or more memory die layers 220. [0026] Among other elements, the system element 210 may include a memory controller 212 corresponding to “a detection circuit” for the memory stack 220.
wherein the detection circuit outputs the detection signal based on whether the upper test pad and the sub-test pad are in contact with each other.
[0028] In some embodiments, the logic chip 210 may include a memory controller, such as a WideIO memory controller “detection circuit”. In some embodiments, the memory controller may address misalignment between ranks by performance throttling, rather than halting memory operation. In delays some embodiments, performance throttling includes the insertion of a time shift to adjust alignment, where a delay may specifically be a one-cycle bubble to shift signal alignment.
Regarding Claims 1, 7, 2, 9, 12-14, Toronyi does not explicitly disclose a sub-test circuit connected to the sub-test pad.
However, in analogous art, Takahashi discloses a method of manufacturing a semiconductor apparatus in which a plurality of semiconductor chips are stacked. [0073] Turning to FIG. 5, two surface bumps 171a and 171b, which are provided in the first memory chip M1, and two test pads TP1a and TP1b are shown. The surface bump 171a and the test pad TP1a are short-circuited. The surface bump 171b and the test pad TP1b are short-circuited. A signal supplied to the test pad TP1a or the surface bump 171a is supplied to the internal circuit 220 (access control circuit 221) of the second memory chip M2.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement a method of manufacturing a semiconductor apparatus in which a plurality of semiconductor chips are stacked as taught by Takahashi in the device and method of Toronyi, since the manufacturing of the stacked semiconductor memory requires a new test process to detect defects in the stacked semiconductor memory. In particular, in the case of a stacked semiconductor memory contained in the SiP, a process of testing a stacked apparatus of semiconductor chips is required, See Takahashi, para.[0005].
Regarding Claims 3-5, and 6, 10, Toronyi does not explicitly disclose the sub-test circuit include a resistor, and a contact connected to a portion of the resistor to extend in a vertical direction; and a connection wire connecting an upper portion of the contact to a lower portion of the sub-test pad.
However, in analogous art, Takahashi discloses para. [0165] The first power-supply line 318 is normally set to off-potential through a resistor R1. The test pad TP1c is also connected to the second memory chip M2 via a through electrode 174c. When the first memory chip M1 is tested, the on-potential is supplied from the test pad TP1c, and test signals are supplied from the test pads TP1a and TP1b. Para. [0166] The second power-supply line 320 is normally set to off-potential through a resistor R2. To the second power-supply line 320, on-potential is supplied from a power-supply control test pad TP2c.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to add a plurality of resistors as taught by Takahashi in the device of Toronyi, as to adjust a power-supply of the power management system.
Regarding Claim 11, Toronyi discloses a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, configured to output a detection signal changed according to a plurality of signals. [0028] FIG. 2. the logic chip 210 may include a memory controller, such as a WideIO memory controller “detection circuit”. In some embodiments, the memory controller may address misalignment between ranks by performance throttling, rather than halting memory operation. [0029] FIG. 3. However, if the rank-to-rank signal relationship becomes sufficiently misaligned, there is a risk of data error or operation that does not meet timing standards. In some embodiments, a one-cycle bubble is inserted to address misalignment without halting data. [0033] In some embodiments, if the misalignment between signals is greater than a certain threshold 615, such as 500 psec for a WideIO memory device, then the memory controller of the memory device operates to throttle the memory operation by inserting one or more one-cycle bubbles to generate sufficient time shift for correction of the misalignment 620.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,183,414. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,183,414, and thus anticipate the Claims of the instant Application, See, Table A. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Table A: Double Patenting Claims comparison
18961956 Instant Application Claims
(U.S. Patent No. 12,183,414) Claims
Independent Claim 1. A memory device comprising:
a memory cell area including a memory cell array; and
a peripheral circuit area overlapping with the memory cell area by bonding to the memory cell area, wherein the peripheral circuit area includes:
a sub-test pad and an input pad spaced apart from each other;
sub-test pad; and
a detection circuit connected to a terminal of the sub-test circuit, the detection circuit being configured to output a detection signal according to a signal input from the terminal,
wherein the memory cell area includes an upper test pad overlapping with a portion of the peripheral circuit area , wherein the upper test pad is bonded and connected to the input pad, and
wherein the detection circuit outputs the detection signal based on whether the upper test pad and the sub-test pad are in contact with each other.
Independent Claim 1. A memory device comprising:
a first chip including a memory cell array; and
a second chip overlapping with the first chip by bonding to the first chip, wherein the second chip includes:
a semiconductor substrate including a peripheral circuit area and a lower test area;
a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other;
a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and
a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit being configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals,
wherein the first chip includes an upper test pad overlapping with a portion of the lower test area of the semiconductor substrate,
wherein the upper test pad is bonded and connected to the input pad and any one of the plurality of sub-test pads, and
wherein the detection circuit outputs the detection signal according to the plurality of signals changed according to which sub-test pad, among the plurality of sub-test pads, the upper test pad is bonded and connected to.
Independent Claim 7. A memory device comprising:
a first chip including a memory area and an upper test area, wherein the memory area includes memory cells; and
a second chip including a peripheral circuit area and a lower test area, wherein the peripheral circuit area includes a peripheral circuit to control the memory cells,
wherein the first chip and the second chip are coupled to each other by wafer bonding and overlap with each other, wherein a plurality of sub-test pads and an input pad are disposed on the lower test area,
wherein an upper test pad is disposed on the upper test area, and wherein the upper test pad is connected to the input pad and at least one of the plurality of sub-test pads.
8. A method of testing a memory device for a failure, the method comprising:
providing a first chip including an upper test pad;
providing a second chip including an input pad, a plurality of sub-test pads arranged at both sides of the input pad to be spaced apart from each other, a plurality of sub-test circuits connected to the sub-test pads, and a detection circuit connected to the plurality of sub-test circuits;
bonding the first chip and the second chip to each other such that the upper test pad and the input pad are connected to each other in a first direction and the upper test pad is connected to any one of the plurality of sub-test pads;
outputting a plurality of signals input to the detection circuit from the plurality of sub-test circuits by inputting a test signal to the input pad; and
determining an alignment error between the first chip and the second chip by checking the one sub-test pad connected to the upper test pad based on a detection signal output from the detection circuit according to the plurality of signals.
Claims 2, 14, wherein the sub-test pad and the input pad are separated by a distance narrower than a width of the upper test pad.
Claim 3, wherein the plurality of sub-test pads and the input pad are separated by a distance narrower than a width of the upper test pad.
Claim 3. wherein the sub-test circuit include a resistor.
Claim 5. wherein the plurality of sub-test circuits includes a plurality of resistors having different resistance values.
Claim 4. wherein the peripheral circuit area further includes a gate insulating layer, and the resistor includes a plurality of conductive patterns disposed on a lower test area with the gate insulating layer interposed therebetween.
Claim 6. wherein the second chip further includes a gate insulating layer on the semiconductor substrate, and the plurality of resistors includes a plurality of conductive patterns disposed on the lower test area of the semiconductor substrate with the gate insulating layer interposed therebetween.
Claim 5. wherein the peripheral circuit area includes a plurality of separation layers, and wherein a lower test area includes a plurality of impurity regions separated from each other by the plurality of separation layers to form the resistor.
Claim 7. wherein the second chip includes a plurality of separation layers formed in the semiconductor substrate, and wherein the lower test area of the semiconductor substrate includes a plurality of impurity regions separated from each other by the plurality of separation layers to respectively form the plurality of resistors.
Claim 6. a contact connected to a portion of the resistor to extend in a vertical direction; and a connection wire connecting an upper portion of the contact to a lower portion of the sub-test pad.
Claim 10. a connection wire connected to one of the plurality of sub-test pads and extending in a vertical direction; a resistor connected to the connection wire; and a terminal connected to the resistor
U.S. Patent No. 12,183,414 does include the limitations of Claims 6 and 10. However, these limitations are described in the specification. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to add a connection wire in the Claims for the purpose of connecting portions of the sub-test pad.
Claim 8. wherein the peripheral circuit includes at least one of a voltage generating circuit, a control circuit, and a page buffer.
Claim 9. wherein the second chip includes a plurality of sub-test circuits respectively connected to the plurality of sub-test pads.
U.S. Patent No. 12,183,414 does include the limitations of Claims 8 and 9. However, these limitations are described in the specification. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to add a voltage generating circuit, and a page buffer in the Claims for generating a signal.
Claim 11. wherein the second chip includes a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.
Claim 14. when the second logic level is input as the test signal to the input pad and the first logic level is output from each of the first to fourth sub-test circuits, an error signal is output as the detection signal.
Claim 12. wherein one or more of the plurality of sub-test pads are disposed at one side of the input pad and remaining sub-test pads of the plurality of sub-test pads are disposed at an other side of the input pad.
Claim 10. whether an electrical connection between each of the plurality of sub-test circuits and the input pad has been made corresponds to whether a connection between each of the plurality of sub-test pads and the upper test pad has been made.
Claim 13. wherein the plurality of sub-test pads and the input pad are spaced apart from each other at a constant distance.
Claim 2. wherein the plurality of sub-test pads and the input pad are spaced apart from each other at a constant distance.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: March 16, 2026
Non-Final Rejection 18961956 20260306
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV